SCPS285A november   2022  – august 2023 TCAL9539-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 I2C Bus Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
      2. 8.3.2 Adjustable Output Drive Strength
      3. 8.3.3 Interrupt Output (INT)
      4. 8.3.4 Reset Input (RESET)
      5. 8.3.5 Software Reset Call
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
    6. 8.6 Register Maps
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register and Command Byte
      3. 8.6.3 Register Descriptions
      4. 8.6.4 Bus Transactions
        1. 8.6.4.1 Writes
        2. 8.6.4.2 Reads
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Minimizing ICC When I/Os Control LEDs
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-On Reset Requirements
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCAL9539-Q1 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 9-6 and Figure 9-7.

GUID-336074CE-FC27-401A-90F5-B53F76557D1B-low.gif Figure 9-6 V is lowered below 0.2 V or 0 V and then ramped up
GUID-76E75F59-7D3A-466F-ADE3-6C85437954DC-low.gif Figure 9-7 V is lowered below the POR threshold, then ramped back up

Table 9-2 specifies the performance of the power-on reset feature for TCAL9539-Q1 for both types of power-on reset.

Table 9-2 Recommended Supply Sequencing and Ramp Rates
PARAMETER(1)(2) MIN TYP MAX UNIT
tFT Fall rate See Figure 9-6 0.1 2000 ms
tRT Rise rate See Figure 9-6 0.1 2000 ms
tTRR_GND Time to re-ramp (when VCC drops to GND) See Figure 9-6 1 μs
tTRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) See Figure 9-7 1 μs
VCC_GH Level that V can glitch down to, but not cause a functional disruption when V = 1 μs See Figure 9-8 1.0 V
tGW Glitch width that will not cause a functional disruption when V = 0.5 × VCCx See Figure 9-8 10 μs
VPORF Voltage trip point of POR on falling VCC 0.6 V
VPORR Voltage trip point of POR on rising VCC 1.0 V
(1) TA = 25°C (unless otherwise noted).
(2) Not tested. Specified by design.

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 9-8 and Table 9-2 provide more information on how to measure these specifications.

GUID-DC1AAB80-A7B0-4E1F-9784-52649EFE7945-low.gif Figure 9-8 Glitch Width and Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the V being lowered to or from 0. Figure 9-9 and Table 9-2 provide more details on this specification.

GUID-F2DF777F-2BD9-4D56-948C-DE93BEF68FF6-low.gif Figure 9-9 VPOR