SLLSF17B August   2019  – October 2021 TCAN1044-Q1 , TCAN1044V-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Characteristics
    6. 6.6  Supply Characteristics
    7. 6.7  Dissipation Ratings
    8. 6.8  Electrical Characteristics
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Description
        1. 8.3.1.1 TXD
        2. 8.3.1.2 GND
        3. 8.3.1.3 VCC
        4. 8.3.1.4 RXD
        5. 8.3.1.5 VIO
        6. 8.3.1.6 CANH and CANL
        7. 8.3.1.7 STB (Standby)
      2. 8.3.2 CAN Bus States
      3. 8.3.3 TXD Dominant Timeout (DTO)
      4. 8.3.4 CAN Bus Short Circuit Current Limiting
      5. 8.3.5 Thermal Shutdown (TSD)
      6. 8.3.6 Undervoltage Lockout
      7. 8.3.7 Unpowered Device
      8. 8.3.8 Floating pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes
      2. 8.4.2 Normal Mode
      3. 8.4.3 Standby Mode
        1. 8.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
      4. 8.4.4 Driver and Receiver Function
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 CAN Termination
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1 Bus Loading, Length and Number of Nodes
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.9 Switching Characteristics

Over recommended operating conditions with TA = -40℃ to 125℃ (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Device Switching Characteristics
tPROP(LOOP1)Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominantNormal mode, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
VIO = 2.8 V to 5.5 V
See Figure 7-4
125210ns
tPROP(LOOP1)Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominantNormal mode, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
VIO = 1.7 V
See Figure 7-4
165255ns
tPROP(LOOP2)Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessiveNormal mode, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
VIO = 2.8 V to 5.5 V
See Figure 7-4
150210ns
tPROP(LOOP2)Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessiveNormal mode, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
VIO = 1.7 V
See Figure 7-4
180255ns
tMODEMode change time, from normal to standby or from standby to normalSee Figure 7-5
20µs
tWK_FILTERFilter time for a valid wake-up patternSee Figure 8-50.51.8µs
tWK_TIMEOUTBus wake-up timeoutSee Figure 8-50.86ms
Driver Switching Characteristics
tpHRPropagation delay time, high TXD to driver recessive (dominant to recessive)STB = 0 V , RL = 60 Ω, CL = 100 pF
See Figure 7-2 and Figure 7-6
80ns
tpLDPropagation delay time, low TXD to driver dominant (recessive to dominant)70ns
tsk(p)Pulse skew (|tpHR - tpLD|)20ns
tRDifferential output signal rise time30ns
tFDifferential output signal fall time50ns
tTXD_DTODominant timeout1.24.0ms
Receiver Switching Characteristics
tpRHPropagation delay time, bus recessive input to high output (dominant to recessive)STB = 0 V , CL(RXD) = 15 pF
See Figure 7-3		90ns
tpDLPropagation delay time, bus dominant input to low output (recessive to dominant)65ns
tRRXD output signal rise time10ns
tFRXD output signal fall time10ns
FD Timing Characteristics
tBIT(BUS)Bit time on CAN bus output pins
tBIT(TXD) = 500 ns		STB = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 7-4		450530ns
tBIT(BUS)Bit time on CAN bus output pins
tBIT(TXD) = 200 ns		155210ns
tBIT(RXD)Bit time on RXD output pins
tBIT(TXD) = 500 ns		400550ns
tBIT(RXD)Bit time on RXD output pins
tBIT(TXD) = 200 ns		120220ns
tRECReceiver timing symmetry
tBIT(TXD) = 500 ns		-5020ns
tRECReceiver timing symmetry
tBIT(TXD) = 200 ns		-4515ns