SPRSPB4C June   2024  – August 2026 TDA4APE-Q1 , TDA4VPE-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      11
      2.      12
    3. 5.3 Signal Descriptions
      1.      14
      2. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
          1.        17
          2.        18
          3.        19
      3. 5.3.2  CPSW2G
        1. 5.3.2.1 MAIN Domain
          1.        22
        2. 5.3.2.2 MCU Domain
          1.        24
      4. 5.3.3  CPTS
        1. 5.3.3.1 MAIN Domain
          1.        27
        2. 5.3.3.2 MCU Domain
          1.        29
      5. 5.3.4  CSI
        1. 5.3.4.1 MAIN Domain
          1.        32
          2.        33
          3.        34
      6. 5.3.5  DDRSS
        1. 5.3.5.1 MAIN Domain
          1.        37
          2.        38
      7. 5.3.6  Display Port
        1. 5.3.6.1 MAIN Domain
          1.        41
      8. 5.3.7  DMTIMER
        1. 5.3.7.1 MAIN Domain
          1.        44
        2. 5.3.7.2 MCU Domain
          1.        46
      9. 5.3.8  DSI
        1. 5.3.8.1 MAIN Domain
          1.        49
          2.        50
      10. 5.3.9  DSS
        1. 5.3.9.1 MAIN Domain
          1.        53
      11. 5.3.10 ECAP
        1. 5.3.10.1 MAIN Domain
          1.        56
          2.        57
          3.        58
      12. 5.3.11 EPWM
        1. 5.3.11.1 MAIN Domain
          1.        61
          2.        62
          3.        63
          4.        64
          5.        65
          6.        66
          7.        67
      13. 5.3.12 EQEP
        1. 5.3.12.1 MAIN Domain
          1.        70
          2.        71
          3.        72
      14. 5.3.13 GPIO
        1. 5.3.13.1 MAIN Domain
          1.        75
        2. 5.3.13.2 WKUP Domain
          1.        77
      15. 5.3.14 GPMC
        1. 5.3.14.1 MAIN Domain
          1.        80
      16. 5.3.15 HYPERBUS
        1. 5.3.15.1 MCU Domain
          1.        83
      17. 5.3.16 I2C
        1. 5.3.16.1 MAIN Domain
          1.        86
          2.        87
          3.        88
          4.        89
          5.        90
          6.        91
          7.        92
        2. 5.3.16.2 MCU Domain
          1.        94
          2.        95
        3. 5.3.16.3 WKUP Domain
          1.        97
      18. 5.3.17 I3C
        1. 5.3.17.1 MCU Domain
          1.        100
      19. 5.3.18 MCAN
        1. 5.3.18.1 MAIN Domain
          1.        103
          2.        104
          3.        105
          4.        106
          5.        107
          6.        108
          7.        109
          8.        110
          9.        111
          10.        112
          11.        113
          12.        114
          13.        115
          14.        116
          15.        117
          16.        118
          17.        119
          18.        120
        2. 5.3.18.2 MCU Domain
          1.        122
          2.        123
      20. 5.3.19 MCASP
        1. 5.3.19.1 MAIN Domain
          1.        126
          2.        127
          3.        128
          4.        129
          5.        130
      21. 5.3.20 MCSPI
        1. 5.3.20.1 MAIN Domain
          1.        133
          2.        134
          3.        135
          4.        136
          5.        137
          6.        138
          7.        139
        2. 5.3.20.2 MCU Domain
          1.        141
          2.        142
      22. 5.3.21 MDIO
        1. 5.3.21.1 MAIN Domain
          1.        145
          2.        146
        2. 5.3.21.2 MCU Domain
          1.        148
      23. 5.3.22 MMC
        1. 5.3.22.1 MAIN Domain
          1.        151
          2.        152
      24. 5.3.23 OSPI
        1. 5.3.23.1 MCU Domain
          1.        155
          2.        156
      25. 5.3.24 PCIE
        1. 5.3.24.1 MAIN Domain
          1.        159
      26. 5.3.25 SERDES
        1. 5.3.25.1 MAIN Domain
          1.        162
          2.        163
          3.        164
      27. 5.3.26 SGMII
        1. 5.3.26.1 MAIN Domain
          1.        167
      28. 5.3.27 UART
        1. 5.3.27.1 MAIN Domain
          1.        170
          2.        171
          3.        172
          4.        173
          5.        174
          6.        175
          7.        176
          8.        177
          9.        178
          10.        179
        2. 5.3.27.2 MCU Domain
          1.        181
        3. 5.3.27.3 WKUP Domain
          1.        183
      29. 5.3.28 UFS
        1. 5.3.28.1 MAIN Domain
          1.        186
      30. 5.3.29 USB
        1. 5.3.29.1 MAIN Domain
          1.        189
      31. 5.3.30 Emulation and Debug
        1. 5.3.30.1 MAIN Domain
          1.        192
          2.        193
      32. 5.3.31 System and Miscellaneous
        1. 5.3.31.1 Boot Mode Configuration
          1.        196
        2. 5.3.31.2 Clock
          1.        198
          2.        199
        3. 5.3.31.3 EFUSE
          1.        201
        4. 5.3.31.4 System
          1.        203
          2.        204
        5. 5.3.31.5 VMON
          1.        206
      33. 5.3.32 Power
        1.       208
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On-Hour (POH) Limits
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Electrical Characteristics
      1. 6.6.1  I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.6.2  Fail-Safe Reset (FS Reset) Electrical Characteristics
      3. 6.6.3  HFOSC/LFOSC Electrical Characteristics
      4. 6.6.4  eMMCPHY Electrical Characteristics
      5. 6.6.5  SDIO Electrical Characteristics
      6. 6.6.6  CSI2/DSI D-PHY Electrical Characteristics
      7. 6.6.7  ADC12B Electrical Characteristics
      8. 6.6.8  LVCMOS Electrical Characteristics
      9. 6.6.9  USB2PHY Electrical Characteristics
      10. 6.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      11. 6.6.11 UFS M-PHY Electrical Characteristics
      12. 6.6.12 eDP/DP AUX-PHY Electrical Characteristics
      13. 6.6.13 DDR0 Electrical Characteristics
    7. 6.7  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8  Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics for AND Package
    9. 6.9  Temperature Sensor Characteristics
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1 Timing Parameters and Information
      2. 6.10.2 Power Supply Sequencing
        1. 6.10.2.1  Power Supply Slew Rate Requirement
        2. 6.10.2.2  Combined MCU and Main Domains Power- Up Sequencing
        3. 6.10.2.3  Combined MCU and Main Domains Power- Down Sequencing - Option 1
        4. 6.10.2.4  Combined MCU and Main Domains Power- Down Sequencing - Option 2
        5. 6.10.2.5  Isolated MCU and Main Domains Power- Up Sequencing
        6. 6.10.2.6  Isolated MCU and Main Domains Power- Down Sequencing - Option 1
        7. 6.10.2.7  Isolated MCU and Main Domains Power- Down Sequencing - Option 2
        8. 6.10.2.8  Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
        9. 6.10.2.9  Independent MCU and Main Domains, Entry and Exit of DDR Retention State
        10. 6.10.2.10 Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
      3. 6.10.3 System Timing
        1. 6.10.3.1 Reset Timing
        2. 6.10.3.2 Safety Signal Timing
        3. 6.10.3.3 Clock Timing
      4. 6.10.4 Clock Specifications
        1. 6.10.4.1 Input and Output Clocks / Oscillators
          1. 6.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 6.10.4.1.1.1 Load Capacitance
            2. 6.10.4.1.1.2 Shunt Capacitance
          2. 6.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 6.10.4.1.3.1 Load Capacitance
            2. 6.10.4.1.3.2 Shunt Capacitance
          4. 6.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.10.4.1.5 Auxiliary OSC1 Not Used
        2. 6.10.4.2 Output Clocks
        3. 6.10.4.3 PLLs
        4. 6.10.4.4 Module and Peripheral Clocks Frequencies
      5. 6.10.5 Peripherals
        1. 6.10.5.1  ATL
          1. 6.10.5.1.1 ATL_PCLK Timing Requirements
          2. 6.10.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.10.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.10.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.10.5.2  CPSW2G
          1. 6.10.5.2.1 CPSW2G MDIO Interface Timings
          2. 6.10.5.2.2 CPSW2G RMII Timings
            1. 6.10.5.2.2.1 CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
            2. 6.10.5.2.2.2 CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
            3. 6.10.5.2.2.3 CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
          3. 6.10.5.2.3 CPSW2G RGMII Timings
            1. 6.10.5.2.3.1 RGMII[x]_RXC Timing Requirements – RGMII Mode
            2. 6.10.5.2.3.2 CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 6.10.5.2.3.3 CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
            4. 6.10.5.2.3.4 RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
        3. 6.10.5.3  CSI-2
        4. 6.10.5.4  DDRSS
        5. 6.10.5.5  DSS
        6. 6.10.5.6  eCAP
          1. 6.10.5.6.1 Timing Requirements for eCAP
          2. 6.10.5.6.2 Switching Characteristics for eCAP
        7. 6.10.5.7  EPWM
          1. 6.10.5.7.1 Timing Requirements for eHRPWM
          2. 6.10.5.7.2 Switching Characteristics for eHRPWM
        8. 6.10.5.8  eQEP
          1. 6.10.5.8.1 Timing Requirements for eQEP
          2. 6.10.5.8.2 Switching Characteristics for eQEP
        9. 6.10.5.9  GPIO
          1. 6.10.5.9.1 GPIO Timing Requirements
          2. 6.10.5.9.2 GPIO Switching Characteristics
        10. 6.10.5.10 GPMC
          1. 6.10.5.10.1 GPMC and NOR Flash — Synchronous Mode
            1. 6.10.5.10.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 6.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 6.10.5.10.2 GPMC and NOR Flash — Asynchronous Mode
            1. 6.10.5.10.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.10.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 6.10.5.10.3 GPMC and NAND Flash — Asynchronous Mode
            1. 6.10.5.10.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 6.10.5.10.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
          4. 6.10.5.10.4 GPMC0 IOSET
        11. 6.10.5.11 HyperBus
          1. 6.10.5.11.1 Timing Requirements for HyperBus
          2. 6.10.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 6.10.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 6.10.5.12 I2C
        13. 6.10.5.13 I3C
        14. 6.10.5.14 MCAN
        15. 6.10.5.15 MCASP
        16. 6.10.5.16 MCSPI
          1. 6.10.5.16.1 MCSPI — Controller Mode
          2. 6.10.5.16.2 MCSPI — Peripheral Mode
        17. 6.10.5.17 MMCSD
          1. 6.10.5.17.1 MMC0 - eMMC Interface
            1. 6.10.5.17.1.1 Legacy SDR Mode
            2. 6.10.5.17.1.2 High Speed SDR Mode
            3. 6.10.5.17.1.3 High Speed DDR Mode
            4. 6.10.5.17.1.4 HS200 Mode
            5. 6.10.5.17.1.5 HS400 Mode
          2. 6.10.5.17.2 MMC1 - SD/SDIO Interface
            1. 6.10.5.17.2.1 Default Speed Mode
            2. 6.10.5.17.2.2 High Speed Mode
            3. 6.10.5.17.2.3 UHS–I SDR12 Mode
            4. 6.10.5.17.2.4 UHS–I SDR25 Mode
            5. 6.10.5.17.2.5 UHS–I SDR50 Mode
            6. 6.10.5.17.2.6 UHS–I DDR50 Mode
            7. 6.10.5.17.2.7 UHS–I SDR104 Mode
        18. 6.10.5.18 CPTS
          1. 6.10.5.18.1 CPTS Timing Requirements
          2. 6.10.5.18.2 CPTS Switching Characteristics
        19. 6.10.5.19 OSPI
          1. 6.10.5.19.1 OSPI0/1 PHY Mode
            1. 6.10.5.19.1.1 OSPI0/1 With PHY Data Training
            2. 6.10.5.19.1.2 OSPI Without Data Training
              1. 6.10.5.19.1.2.1 OSPI Timing Requirements – SDR Mode
              2. 6.10.5.19.1.2.2 OSPI Switching Characteristics – SDR Mode
              3. 6.10.5.19.1.2.3 OSPI Timing Requirements – DDR Mode
              4. 6.10.5.19.1.2.4 OSPI Switching Characteristics – PHY DDR Mode
          2. 6.10.5.19.2 OSPI0/1 Tap Mode
            1. 6.10.5.19.2.1 OSPI0 Tap SDR Timing
            2. 6.10.5.19.2.2 OSPI0 Tap DDR Timing
        20. 6.10.5.20 OLDI
          1. 6.10.5.20.1 OLDI Switching Characteristics
        21. 6.10.5.21 PCIE
        22. 6.10.5.22 Timers
          1. 6.10.5.22.1 Timing Requirements for Timers
          2. 6.10.5.22.2 Switching Characteristics for Timers
        23. 6.10.5.23 UART
          1. 6.10.5.23.1 Timing Requirements for UART
          2. 6.10.5.23.2 UART Switching Characteristics
        24. 6.10.5.24 USB
      6. 6.10.6 Emulation and Debug
        1. 6.10.6.1 Trace
        2. 6.10.6.2 JTAG
          1. 6.10.6.2.1 JTAG Electrical Data and Timing
            1. 6.10.6.2.1.1 JTAG Timing Requirements
            2. 6.10.6.2.1.2 JTAG Switching Characteristics
  8. 7 Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 7.1.1.1 Power Distribution Network Implementation Guidance
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG and EMU
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 Hardware Design Guide for JacintoTM 7 Devices
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 LPDDR4 Board Design and Layout Guidelines
      2. 7.2.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 7.2.2.1 No Loopback and Internal Pad Loopback
        2. 7.2.2.2 External Board Loopback
        3. 7.2.2.3 DQS (only available in Octal Flash devices)
      3. 7.2.3 USB VBUS Design Guidelines
      4. 7.2.4 System Power Supply Monitor Design Guidelines using VMON/POK
      5. 7.2.5 High Speed Differential Signal Routing Guidance
      6. 7.2.6 Thermal Solution Guidance
  9. 8 Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • AND|1063
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4 Pin Connectivity Requirements

This section describes connectivity requirements for package balls that have specific connectivity requirements and unused package balls.

Note:

All power balls must be supplied with the voltages specified in the Recommended Operating Conditions section, unless otherwise specified in Signal Descriptions.

Note:

For additional clarification, "leave unconnected" or "no connect" (NC) means no signal traces can be connected to these device ball number.

Table 5-118 shows the connectivity requirements for specific signals by ball name and ball number.

Table 5-118 Connectivity Requirements
BALL
NUMBER		 BALL NAME CONNECTION REQUIREMENT
B23 OSC1_XI Each of these balls must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low-level, if unused.
A24 WKUP_OSC0_XI
F17 TRSTN
R1 DDR0_DQS0P
V1 DDR0_DQS1P
AD1 DDR0_DQS2P
AG1 DDR0_DQS3P
B1 DDR1_DQS0P
E1 DDR1_DQS1P
L1 DDR1_DQS2P
P1 DDR1_DQS3P
AC7 DDR0_RET
G8 DDR1_RET
G26 VMON1_ER_VSYS
L25 VMON2_IR_VCPU
K30 VMON3_IR_VEXT1P8
M26 VMON4_IR_VEXT1P8
M29 VMON5_IR_VEXT3P3
E26 MCU_ADC0_AIN0 Each of these balls can be connected to VSS through a separate external pull resistor or can be connected directly to VSS to ensure these balls are held to a valid logic low-level, if unused.
F25 MCU_ADC0_AIN1
F23 MCU_ADC0_AIN2
A28 MCU_ADC0_AIN3
E24 MCU_ADC0_AIN4
D27 MCU_ADC0_AIN5
A26 MCU_ADC0_AIN6
B27 MCU_ADC0_AIN7
C32 MCU_ADC1_AIN0
B33 MCU_ADC1_AIN1
B31 MCU_ADC1_AIN2
B29 MCU_ADC1_AIN3
D31 MCU_ADC1_AIN4
A32 MCU_ADC1_AIN5
A30 MCU_ADC1_AIN6
C28 MCU_ADC1_AIN7
AG7 SERDES0_REXT Each of these balls must be connected to VSS through appropriate external pull resistor to ensure these balls are held to a valid logic low level, if unused. Refer to Signal Descriptions footnote for appropriate value of pull-resistor for each signal.
AH9 SERDES1_REXT
AH23 SERDES4_REXT
AH31 CSI0_RXRCALIB
AJ33 CSI1_RXRCALIB
AH29 CSI2_RXRCALIB
R7 DDR0_CAL0
F8 DDR1_CAL0
AH25 DSI0_TXRCALIB
AH27 DSI1_TXRCALIB
AH22 USB0_RCALIB
E20 MCU_RESETZ Each of these balls must be connected to the corresponding power supply through a separate external pull resistor to ensure these balls are held to a valid logic high level, if unused.
C24 MCU_PORZ
D24 PORZ
G20 RESET_REQZ
F21 TCK
V32 TMS
A21 MCU_I2C0_SDA
D22 MCU_I2C0_SCL
A16 WKUP_I2C0_SCL
D23 WKUP_I2C0_SDA
AA30 I2C0_SCL
Y30 I2C0_SDA
Y29 EXTINTn
V33 TDI
W33 TDO
F19 EMU0
E17 EMU1
T1 DDR0_DQS0N
W1 DDR0_DQS1N
AC1 DDR0_DQS2N
AF1 DDR0_DQS3N
C1 DDR1_DQS0N
F1 DDR1_DQS1N
K1 DDR1_DQS2N
N1 DDR1_DQS3N
D25 MCU_ADC0_REFP If the MCU_ADCn interface is not used, these signals should be connected to the same power supply as the VDDA_ADCn supply input.
C30 MCU_ADC1_REFP
C26 MCU_ADC0_REFN If the MCU_ADCn interface is not used, these signals should be connected to VSS.
D29 MCU_ADC1_REFN
F26 VPP_MCU Each of these balls must be left unconnected, if unused.
V29 VPP_CORE
AH2 MMC0_CALPAD
DDR0_* DDRSS0 and DDRSS1 must always be used in incremental order. For instance, when using a single LPDDR component, it must be connected to the DDR0_* interface. When using two LPDDR components, they must be connected to DDR0_* and DDR1_* interfaces.
DDR1_*

Table 5-119 shows the specific connection requirements for the RESERVED ball numbers on the device.

Note:

For additional clarification, "left unconnected" or "no connect" (NC) means no signal traces can be connected to these device ball numbers.

Table 5-119 Reserved Balls Specific Connection Requirements
BALL NUMBERS CONNECTION REQUIREMENTS
E28 / F27 / J29 / L28 / L29 / L30 / M30 / AH4 / AH7 / AH8 RESERVED.
These balls must be left unconnected.
Note:

All other unused signal balls without Pad Configuration Register can be left unconnected.

Note:

All other unused signal balls with a Pad Configuration Register can be left unconnected with their multiplexing mode set to GPIO input and internal pulldown resistor enabled.

Unused balls are defined as those which only connect to a PCB solder pad. This is the only use case where internal pull resistors are allowed as the only source/sink to hold a valid logic level.

Any balls connected to a via, test point, or PCB trace are considered used and must not depend on the internal pull resistor to hold a valid logic level.

Internal pull resistors are weak and may not source enough current to maintain a valid logic level for some operating conditions. This may be the case when connected to components with leakage to the opposite logic level, or when external noise sources couple to signal traces attached to balls which are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors may be required to hold a valid logic level on balls with external connections.