SLLSF20B July   2019  – October 2021 THVD2410 , THVD2450

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings [IEC]
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Dissipation
    7. 6.7  Electrical Characteristics
    8. 6.8  Switching Characteristics: THVD2410
    9. 6.9  Switching Characteristics: THVD2450
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 ±70-V Fault Protection
      2. 8.3.2 Integrated IEC ESD and EFT Protection
      3. 8.3.3 Driver Overvoltage and Overcurrent Protection
      4. 8.3.4 Enhanced Receiver Noise Immunity
      5. 8.3.5 Receiver Fail-Safe Operation
      6. 8.3.6 Low-Power Shutdown Mode
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Transient Protection
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 D (SOIC) and DGK (VSSOP), 8-Pin Packages, Top View
Figure 5-2 DRB (VSON), 8-Pin Package, Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME D DGK DRB
A 6 6 6 Bus input/output Bus I/O port, A (complementary to B)
B 7 7 7 Bus input/output Bus I/O port, B (complementary to A)
D 4 4 4 Digital input Driver data input
DE 3 3 3 Digital input Driver enable, active high (2-MΩ internal pull-down)
GND 5 5 5 Ground Device ground
R 1 1 1 Digital output Receive data output
VCC 8 8 8 Power 3.3-V to 5-V supply
RE 2 2 2 Digital input Receiver enable, active low (2-MΩ internal pull-up)
Thermal Pad — — — — No electrical connection. Should be connected to GND plane for optimal thermal performance