In order for TL43xLI to properly be used as a comparator, the logic output must be readable by the receiving logic device. This is accomplished by knowing the input high and low level threshold voltage levels, typically denoted by VIH and VIL.
As seen in Figure 21, TL43xLI's output low level voltage in open-loop/comparator mode is approximately 2 V, which is typically sufficient for 5 V supplied logic. However, would not work for 3.3 V and 1.8 V supplied logic. To accommodate this a resistive divider can be tied to the output to attenuate the output voltage to a voltage legible to the receiving low voltage logic device.
TL43xLI's output high voltage is equal to VSUP due to TL43xLI being open-collector. If VSUP is much higher than the receiving logic's maximum input voltage tolerance, the output must be attenuated to accommodate the outgoing logic's reliability.
When using a resistive divider on the output, be sure to make the sum of the resistive divider (R1 and R2 in Figure 20) is much greater than RSUP in order to not interfere with TL43xLI's ability to pull close to VSUP when turning off.