SLVS814A January   2008  – May 2015 TLC5916-Q1 , TLC5917-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: VDD = 3 V
    6. 7.6  Electrical Characteristics: VDD = 5.5 V
    7. 7.7  Timing Requirements
    8. 7.8  Switching Characteristics: VDD = 3 V
    9. 7.9  Switching Characteristics: VDD = 5.5 V
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Open-Circuit Detection Principle
      2. 9.3.2 Short-Circuit Detection Principle (TLC5917-Q1 Only)
      3. 9.3.3 Overtemperature Detection and Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation Mode Switching
        1. 9.4.1.1 Normal Mode Phase
        2. 9.4.1.2 Special Mode Phase
    5. 9.5 Programming
      1. 9.5.1 Reading Error Status Code in Special Mode
      2. 9.5.2 Writing Configuration Code in Special Mode
      3. 9.5.3 8-Bit Configuration Code and Current Gain
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Constant Current
      2. 10.1.2 Adjusting Output Current
    2. 10.2 Typical Applications
      1. 10.2.1 Single Implementation of TLC591x-Q1 Device
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Cascading Implementation of TLC591x-Q1 Device
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VDD(2) Supply voltage 0 7 V
VI(3) Input voltage –0.4 VDD + 0.4 V
VO(4) Output voltage –0.5 20 V
fclk Clock frequency 25 MHz
IOUT Output current 120 mA
IGND GND terminal current 960 mA
TA Operating free-air temperature –40 125 °C
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
(3) Absolute negative voltage on these terminals must not go below 0 V.
(4) Absolute maximum voltage is 7 V for 200 ms.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±1500 V
Charged device model (CDM), per AEC Q100-011 Other pins ±1000
Corner pins (GND, OUT3, VDD, and OUT4) ±1000
Machine Model ±150
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD Supply voltage 3 5.5 V
VO Supply voltage to output pins OUT0–OUT7 17 V
IO Output current DC test circuit VO ≥ 0.6 V 5 mA
VO ≥ 1 V 120
IOH High-level output current source SDO shorted to GND –1 mA
IOL Low-level output current sink SDO shorted to VCC 1 mA
VIH High-level input voltage CLK, OE(ED2), LE(ED1), and SDI 0.7 × VDD VDD V
VIL Low-level input voltage CLK, OE(ED2), LE(ED1), and SDI 0 0.3 × VDD V

7.4 Thermal Information

THERMAL METRIC(1) TLC591x-Q1 UNIT
D (SOIC)
16 PINS
RθJA Junction-to-ambient thermal resistance 86.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 47.7 °C/W
RθJB Junction-to-board thermal resistance 43.9 °C/W
ψJT Junction-to-top characterization parameter 11.9 °C/W
ψJB Junction-to-board characterization parameter 43.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: VDD = 3 V

VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT
VDD Input voltage 3 5.5 V
VO Supply voltage to the output pins 17 V
IO Output current VO ≥ 0.6 V 5 mA
VO ≥ 1 V 120
IOH High-level output current, source –1 mA
IOL Low-level output current, sink 1 mA
VIH High-level input voltage 0.7 × VDD VDD V
VIL Low-level input voltage GND 0.3 × VDD V
Ileak Output leakage current VOH = 17 V TJ = 25°C 0.5 μA
TJ = 125°C 2
VOH High-level output voltage SDO, IOL = –1 mA VDD – 0.4 V
VOL Low-level output voltage SDO, IOH = 1 mA 0.4 V
IO(1) Output current 1 VOUT = 0.6 V, Rext = 720 Ω, CG = 0.992 26 mA
Output current error, die-die IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C ±3% ±6%
Output current skew, channel-to-channel IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C ±1.5% ±3%
IO(2) Output current 2 VO = 0.8 V, Rext = 360 Ω, CG = 0.992 52 mA
Output current error, die-die IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C ±2% ±6%
Output current skew, channel-to-channel IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C ±1.5% ±3%
IOUT vs VOUT Output current vs output voltage regulation VO = 1 V to 3  V, IO = 26 mA ±0.1 %/V
VDD = 3 V to 5.5 V, IO = 26 mA/120 mA ±1
Pullup resistance OE(ED2) 500 kΩ
Pulldown resistance LE(ED1) 500 kΩ
Tsd Overtemperature shutdown(1) 150 175 200 °C
Thys Restart temperature hysteresis 15 °C
IOUT,Th1 Threshold current for open error detection IOUT,target = 26 mA 0.5 × Itarget%
IOUT,Th2 Threshold current for open error detection IOUT,target = 52 mA 0.5 × Itarget%
IOUT,Th3 Threshold current for open error detection IOUT,target = 104 mA 0.5 × Itarget%
IOUT,Th Threshold current for open error detection IOUT,target = 5 mA to 120 mA 0.5 × Itarget%
VOUT,TTh Trigger threshold voltage for short-error detection (TLC5917-Q1 only) IOUT,target = 5 mA to 120 mA 2.44 2.7 3.1 V
VOUT,RTh Return threshold voltage for short-error detection (TLC5917-Q1 only) IOUT,target = 5 mA to 120 mA 2.2 V
IDD Supply current Rext = Open 5 10 mA
Rext = 720 Ω 8 14
Rext = 360 Ω 11 18
Rext = 180 Ω 16 22
(1) Specified by design
(2) Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the application and configuration and may vary over time. Typical values are not ensured on production material.

7.6 Electrical Characteristics: VDD = 5.5 V

VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VDD Input Voltage 3 5.5 V
VO Supply voltage to the output pins 17 V
IO Output current VO ≥ 0.6 V 5 mA
VO ≥ 1 V 120
IOH High-level output current, source –1 mA
IOL Low-level output current, sink 1 mA
VIH High-level input voltage 0.7 × VDD VDD V
VIL Low-level input voltage GND 0.3 × VDD V
Ileak Output leakage current VOH = 17 V TJ = 25°C 0.5 μA
TJ = 125°C 2
VOH High-level output voltage SDO, IOL = –1 mA VDD – 0.4 V
VOL Low-level output voltage SDO, IOH = 1 mA 0.4 V
IO(1) Output current 1 VOUT = 0.6 V, Rext = 720 Ω, CG = 0.992 26 mA
Output current error, die-die IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C ±3% ±6%
Output current skew, channel-to-channel IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C ±1.5% ±3%
IO(2) Output current 2 VO = 0.8 V, Rext = 360 Ω, CG = 0.992 52 mA
Output current error, die-die IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C ±2% ±6%
Output current skew, channel-to-channel IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C ±1.5% ±3%
IOUT vs VOUT Output current vs output voltage regulation VO = 1 V to 3 V , IO = 26 mA ±0.1 %/V
VDD = 3 V to 5.5 V, IO = 26 mA/120 mA ±1
Pullup resistance OE(ED2), 500 kΩ
Pulldown resistance LE(ED1), 500 kΩ
Tsd Overtemperature shutdown(2) 150 175 200 °C
Thys Restart temperature hysteresis 15 °C
IOUT,Th1 Threshold current for open error detection IOUT,target = 26 mA 0.5 × Itarget%
IOUT,Th2 Threshold current for open error detection IOUT,target = 52 mA 0.5 × Itarget%
IOUT,Th3 Threshold current for open error detection IOUT,target = 104 mA 0.5 × Itarget%
IOUT,Th Threshold current for open error detection IOUT,target = 5 mA to 120 mA 0.5 × Itarget%
VOUT,TTh Trigger threshold voltage for short-error detection (TLC5917-Q1 only) IOUT,target = 5 mA to 120 mA 2.44 2.7 3.1 V
VOUT,RTh Return threshold voltage for short-error detection (TLC5917-Q1 only) IOUT,target = 5 mA to 120 mA 2.2 V
IDD Supply current Rext = Open 6 10 mA
Rext = 720 Ω 11 14
Rext = 360 Ω 13 18
Rext = 180 Ω 19 24
(1) Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the application and configuration and may vary over time. Typical values are not ensured on production material.
(2) Specified by design

7.7 Timing Requirements

VDD = 3 V to 5.5 V (unless otherwise noted)
MIN NOM MAX UNIT
tw(L) LE(ED1) pulse duration Normal mode 20 ns
tw(CLK) CLK pulse duration Normal mode 20 ns
tw(OE) OE(ED2) pulse duration Normal mode, IOUT < 60 mA 675 ns
Normal mode, IOUT > 60 mA 800
tsu(D) Setup time for SDI Normal mode 3 ns
th(D) Hold time for SDI Normal mode 2 ns
tsu(L) Setup time for LE(ED1) Normal mode 15 ns
th(L) Hold time for LE(ED1) Normal mode 15 ns
tw(CLK) CLK pulse duration Error Detection mode 20 ns
tw(ED2) OE(ED2) pulse duration Error Detection mode 2000 ns
tsu(ED1) Setup time for LE(ED1) Error Detection mode 4 ns
th(ED1) Hold time for LE(ED1) Error Detection mode 10 ns
tsu(ED2) Setup time for OE(ED2) Error Detection mode 8.5 ns
th(ED2) Hold time for OE(ED2) Error Detection mode 10 ns
fCLK Clock frequency Cascade operation 30 MHz

7.8 Switching Characteristics: VDD = 3 V

VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPLH1 Low-to-high propagation delay time, CLK to OUTn VIH = VDD, VIL = GND, Rext = 360 Ω, VL = 4 V, RL = 44 Ω, CL = 10 pF, CG = 0.992 40 65 95 ns
tPLH2 Low-to-high propagation delay time, LE(ED1) to OUTn 40 65 95 ns
tPLH3 Low-to-high propagation delay time, OE(ED2) to OUTn 40 65 95 ns
tPLH4 Low-to-high propagation delay time, CLK to SDO 12 20 30 ns
tPHL1 High-to-low propagation delay time, CLK to OUTn 300 365 ns
tPHL2 High-to-low propagation delay time, LE(ED1) to OUTn 300 365 ns
tPHL3 High-to-low propagation delay time, OE(ED2) to OUTn 300 365 ns
tPHL4 High-to-low propagation delay time, CLK to SDO 12 20 30 ns
tw(CLK) Pulse duration, CLK 20 ns
tw(L) Pulse duration, LE(ED1) 20 ns
tw(OE) Pulse duration, OE(ED2) 500 ns
tw(ED2) Pulse duration, OE(ED2) in Error Detection mode 2 μs
th(ED1,ED2) Hold time, LE(ED1) and OE(ED2) 10 ns
th(D) Hold time, SDI 2 ns
tsu(D,ED1) Setup time, SDI, LE(ED1) 4 ns
tsu(ED2) Setup time, OE(ED2) 8.5 ns
th(L) Hold time, LE(ED1), Normal mode 15 ns
tsu(L) Setup time, LE(ED1), Normal mode 15 ns
tr Rise time, CLK(2) 500 ns
tf Fall time, CLK(2) 500 ns
tor Rise time, outputs (off) 40 85 105 ns
tor Rise time, outputs (off), TJ = 25°C 83 100 ns
tof Rise time, outputs (on) 100 280 370 ns
tof Rise time, outputs (on), TJ = 25°C 170 225 ns
fCLK Clock frequency Cascade operation 30 MHz
(1) Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the application and configuration and may vary over time. Typical values are not ensured on production material.
(2) If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices.

7.9 Switching Characteristics: VDD = 5.5 V

VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPLH1 Low-to-high propagation delay time, CLK to OUTn VIH = VDD, VIL = GND, Rext = 360 Ω, VL = 4 V, RL = 44 Ω, CL = 10 pF, CG = 0.992 40 65 95 ns
tPLH2 Low-to-high propagation delay time, LE(ED1) to OUTn 40 65 95 ns
tPLH3 Low-to-high propagation delay time, OE(ED2) to OUTn 40 65 95 ns
tPLH4 Low-to-high propagation delay time, CLK to SDO 8 20 30 ns
tPHL1 High-to-low propagation delay time, CLK to OUTn 300 365 ns
tPHL2 High-to-low propagation delay time, LE(ED1) to OUTn 300 365 ns
tPHL3 High-to-low propagation delay time, OE(ED2) to OUTn 300 365 ns
tPHL4 High-to-low propagation delay time, CLK to SDO 8 20 30 ns
tw(CLK) Pulse duration, CLK 20 ns
tw(L) Pulse duration, LE(ED1) 20 ns
tw(OE) Pulse duration, OE(ED2) 500 ns
tw(ED2) Pulse duration, OE(ED2) in Error Detection mode 2 μs
th(D,ED1,ED2) Hold time, SDI, LE(ED1), and OE(ED2) 10 ns
th(D) Hold time, SDI 2 ns
tsu(D,ED1) Setup time, SDI, LE(ED1) 4 ns
tsu(ED2) Setup time, OE(ED2) 8.5 ns
th(L) Hold time, LE(ED1), Normal mode 15 ns
tsu(L) Setup time, LE(ED1), Normal mode 15 ns
tr Rise time, CLK(2) 500 ns
tf Fall time, CLK(2) 500 ns
tor Rise time, outputs (off) 40 85 105 ns
tor Rise time, outputs (off), TJ = 25°C 83 100 ns
tof Rise time, outputs (on) 100 280 370 ns
tof Rise time, outputs (on), TJ = 25°C 170 225 ns
fCLK Clock frequency Cascade operation 30 MHz
(1) Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the application and configuration and may vary over time. Typical values are not ensured on production material.
(2) If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices.

7.10 Typical Characteristics

TLC5916-Q1 TLC5917-Q1 g_resp_clk_out_lvs814.gif
Figure 1. Response Time, CLK to OUTn
TLC5916-Q1 TLC5917-Q1 g_resp_oe_out_ch8_lvs814.gif
Figure 3. Response Time, OE to OUT7
TLC5916-Q1 TLC5917-Q1 g_resp_oe_out_ch1_lvs814.gif
Figure 2. Response Time, OE to OUT1