SLVS765B October   2008  – September 2015 TLC5925

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: VDD = 3 V
    6. 6.6  Electrical Characteristics: VDD = 5.5 V
    7. 6.7  Power Dissipation and Thermal Impedance
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics: VDD = 3 V
    10. 6.10 Switching Characteristics: VDD = 5.5 V
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Constant Current
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Turning on the LEDs
      2. 9.1.2 Propagation Delay Times
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Adjusting Output Current
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VDD Supply voltage 0 7 V
VI Input voltage –0.4 VDD + 0.4 V
VO Output voltage –0.5 20 V
IOUT Output current 45 mA
IGND GND terminal current 750 mA
TA Free-air operating temperature range –40 125 °C
TJ Operating junction temperature range –40 150 °C
Tstg Storage temperature range –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD Supply voltage 3 5.5 V
VO Output voltage OUT0 to OUT15 17 V
IO Output current DC test circuit VO ≥ 0.6 V 3 mA
VO ≥ 1 V 45
IOH High-level output current SDO –1 mA
IOL Low-level output current SDO 1 mA
VIH High-level input voltage CLK, OE, LE, and SDI 0.7 × VDD VDD V
VIL Low-level input voltage CLK, OE, LE, and SDI GND 0.3 × VDD V
tR Rise Time CLK 500 ns
tF Fall Time CLK 500 ns

6.4 Thermal Information

THERMAL METRIC (1) TLC5925 UNIT
DBQ (SSOP) DW (SOIC) PW (TSSOP)
24 PINS 24 PINS 24 PINS
RθJA Junction-to-ambient thermal resistance Mounted on JEDEC 1-layer board (JESD 51-3), No airflow 99.8 80.5 118.8 °C/W
Mounted on JEDEC 4-layer board (JESD 51-7), No airflow 61 45.5 87.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 52.9 45.0 44.9 °C/W
RθJB Junction-to-board thermal resistance 41.5 44.8 52.9 °C/W
ψJT Junction-to-top characterization parameter 16.4 21.7 6.7 °C/W
ψJB Junction-to-board characterization parameter 41.2 44.4 52.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics: VDD = 3 V

VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Input voltage 3 5.5 V
VO Output voltage 17 V
IO Output current VO ≥ 0.6 V 3 mA
VO ≥ 1 V 45
IOH High-level output current, source -1 mA
IOL Low-level output current, sink 1
VIH High-level input voltage 0.7 × VDD VDD V
VIL Low-level input voltage GND 0.3 × VDD
Ileak Output leakage current VOH = 17 V TJ = 25°C 0.5 μA
TJ = 125°C 2
VOH High-level output voltage SDO, IOL = –1 mA VDD – 0.4 V
VOL Low-level output voltage SDO, IOH = 1 mA 0.4 V
IO(1) Output current 1 VOUT = 0.6 V, Rext = 1680 Ω 13 mA
Output current error, die-die IOL = 13 mA, VO = 0.6 V, Rext = 1680 Ω, TJ = 25°C ±3% ±6%
Output current error, channel-to-channel IOL = 13 mA, VO = 0.6 V, Rext = 1680 Ω, TJ = 25°C ±1.5% ±4%
IO(2) Output current 2 VO = 0.8 V, Rext = 840 Ω 26 mA
Output current error, die-die IOL = 26 mA, VO = 0.8 V, Rext = 840 Ω, TJ = 25°C ±3% ±6%
Output current error, channel-to-channel IOL = 26 mA, VO = 0.8 V, Rext = 840 Ω, TJ = 25°C ±1.5% ±4%
IOUT vs VOUT Output current vs output voltage regulation VO = 1 V to 3  V, IO = 13 mA ±0.1 %/V
VDD = 3.0 V to 5.5 V, IO = 13 mA to 45 mA ±1
Pullup resistance OE 500 kΩ
Pulldown resistance LE 500 kΩ
Tsd Overtemperature shutdown (1) 150 175 200 °C
Thys Restart temperature hysteresis 15 °C
IDD Supply current Rext = Open 7 10 mA
Rext = 1680 Ω 9 12
Rext = 840 Ω 11 13
CIN Input capacitance VI = VDD or GND, CLK, SDI, SDO, OE 10 pF
(1) Specified by design

6.6 Electrical Characteristics: VDD = 5.5 V

VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Input voltage 3 5.5 V
VO Output voltage 17 V
IO Output current VO ≥ 0.6 V 3 mA
VO ≥ 1 V 45
IOH High-level output current, source -1 mA
IOL Low-level output current, sink 1
VIH High-level input voltage 0.7 × VDD VDD V
VIL Low-level input voltage GND 03 × VDD
Ileak Output leakage current VOH = 17 V TJ = 25°C 0.5 μA
TJ = 125°C 2
VOH High-level output voltage SDO, IOL = –1 mA VDD – 0.4 V
VOL Low-level output voltage SDO, IOH = 1 mA 0.4 V
IO(1) Output current 1 VOUT = 0.6 V, Rext = 1680 Ω 13 mA
Output current error, die-die IOL = 13 mA, VO = 0.6 V, Rext = 1680 Ω, TJ = 25°C ±3$ ±6$
Output current error, channel-to-channel IOL = 13 mA, VO = 0.6 V, Rext = 1680 Ω, TJ = 25°C ±1.5$ ±4$
IO(2) Output current 2 VO = 0.8 V, Rext = 840 Ω 26 mA
Output current error, die-die IOL = 26 mA, VO = 0.8 V, Rext = 840 Ω, TJ = 25°C ±3% ±6%
Output current error, channel-to-channel IOL = 26 mA, VO = 0.8 V, Rext = 840 Ω, TJ = 25°C ±1.5% ±4%
IOUT vs VOUT Output current vs output voltage regulation VO = 1 V to 3 V , IO = 26 mA ±0.1 %/V
VDD = 3.0 V to 5.5 V, IO = 13 mA to 45 mA ±1
Pullup resistance OE 500 kΩ
Pulldown resistance LE 500 kΩ
Tsd Overtemperature shutdown (1) 150 175 200 °C
Thys Restart temperature hysteresis 15 °C
IDD Supply current Rext = Open 9 11 mA
Rext = 1680 Ω 12 14
Rext = 840 Ω 14 16
CIN Input capacitance VI = VDD or GND, CLK, SDI, SDO, OE 10 pF
(1) Specified by design

6.7 Power Dissipation and Thermal Impedance

MIN MAX UNIT
PD Power dissipation Mounted on JEDEC 4-layer board (JESD 51-7), No airflow, TA = 25°C, TJ = 125°C DBQ package 1.6 W
DW package 2.2
PW package 1.1

6.8 Timing Requirements

VDD = 3 V to 5.5 V (unless otherwise noted)
MIN MAX UNIT
tw(L) LE pulse duration 15 ns
tw(CLK) CLK pulse duration 15 ns
tw(OE) OE pulse duration 300 ns
tsu(D) Setup time for SDI 3 ns
th(D) Hold time for SDI 2 ns
tsu(L) Setup time for LE 5 ns
th(L) Hold time for LE 5 ns
fCLK Clock frequency, Cascade operation 30 MHz

6.9 Switching Characteristics: VDD = 3 V

VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH1 Low-to-high propagation delay time, CLK to OUTn VIH = VDD, VIL = GND,
Rext = 840 Ω, VL = 4 V,
RL = 88 Ω, CL = 10 pF		 30 45 60 ns
tPLH2 Low-to-high propagation delay time, LE to OUTn 30 45 60 ns
tPLH3 Low-to-high propagation delay time, OE to OUTn 30 45 60 ns
tPLH4 Low-to-high propagation delay time, CLK to SDO 30 40 ns
tPHL1 High-to-low propagation delay time, CLK to OUTn 40 65 100 ns
tPHL2 High-to-low propagation delay time, LE to OUTn 40 65 100 ns
tPHL3 High-to-low propagation delay time, OE to OUTn 40 65 100 ns
tPHL4 High-to-low propagation delay time, CLK to SDO 30 40 ns
tw(CLK) Pulse duration, CLK 15 ns
tw(L) Pulse duration LE 15 ns
tw(OE) Pulse duration, OE 300 ns
th(D) Hold time, SDI 2 ns
tsu(D) Setup time, SDI 3 ns
th(L) Hold time, LE 5 ns
tsu(L) Setup time, LE 5 ns
tr Rise time, CLK (1) 500 ns
tf Fall time, CLK (1) 500 ns
tor Rise time, outputs (off) 35 50 70 ns
tof Rise time, outputs (on) 15 50 120 ns
fCLK Clock frequency Cascade operation 30 MHz
(1) If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices.

6.10 Switching Characteristics: VDD = 5.5 V

VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH1 Low-to-high propagation delay time, CLK to OUTn VIH = VDD, VIL = GND,
Rext = 840 Ω, VL = 4 V,
RL = 88 Ω, CL = 10 pF		 20 35 55 ns
tPLH2 Low-to-high propagation delay time, LE to OUTn 20 35 55 ns
tPLH3 Low-to-high propagation delay time, OE to OUTn 20 35 55 ns
tPLH4 Low-to-high propagation delay time, CLK to SDO 20 30 ns
tPHL1 High-to-low propagation delay time, CLK to OUTn 15 28 42 ns
tPHL2 High-to-low propagation delay time, LE to OUTn 15 28 42 ns
tPHL3 High-to-low propagation delay time, OE to OUTn 15 28 42 ns
tPHL4 High-to-low propagation delay time, CLK to SDO 20 30 ns
tw(CLK) Pulse duration, CLK 10 ns
tw(L) Pulse duration LE 10 ns
tw(OE) Pulse duration, OE 200 ns
th(D) Hold time, SDI 2 ns
tsu(D) Setup time, SDI 3 ns
th(L) Hold time, LE 5 ns
tsu(L) Setup time, LE 5 ns
tr Rise time, CLK (1) 500 ns
tf Fall time, CLK (1) 500 ns
tor Rise time, outputs (off) 25 45 65 ns
tof Rise time, outputs (on) 7 12 20 ns
fCLK Clock frequency Cascade operation 30 MHz
(1) If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices.
TLC5925 t_normal_mode_lvs765.gif Figure 1. Timing Diagram

6.11 Typical Characteristics

TLC5925 g_iout_vout_lvs765.gif Figure 2. Output Current vs Output Voltage