SLVSCE7A
May 2014 – September 2014
TLC5958
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Typical Application Circuit (Multiple Daisy-Chained TLC5958s)
5
Revision History
6
Description (Continued)
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
Handling Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Typical Characteristics
9
Parameter Measurement Information
9.1
Pin Equivalent Input and Output Schematic Diagrams
9.1.1
Test Circuits
9.2
Timing Diagrams
10
Detailed Description
10.1
Overview
10.2
Functional Block Diagram
10.3
Device Functional Modes
10.3.1
Brightness Control (BC) Function
10.3.2
Color Brightness Control (CC) Function
10.3.3
Select RIREF For a Given BC
10.3.4
Choosing BC/CC For a Different Application
10.3.4.1
Example 1: Red LED Current is 20mA, Green LED Needs 12mA, Blue LED needs 8mA
10.3.4.2
Example 2: Red LED Current is 5mA, Green LED Needs 2mA, Blue LED Needs 1mA.
10.3.5
LED Open Detection (LOD)
10.3.6
Power Save Mode (PSM)
10.3.7
Internal Pre-Charge FET
10.3.8
Thermal Shutdown (TSD)
10.3.9
IREF Resistor Short Protection (ISP)
10.3.10
Noise Reduction
11
Application and Implementation
12
Power Supply Recommendations
13
Layout
13.1
Layout Guidelines
13.2
Layout Example
14
Device and Documentation Support
14.1
Trademarks
14.2
Electrostatic Discharge Caution
14.3
Glossary
15
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RTQ|56
MPQF168D
Thermal pad, mechanical data (Package|Pins)
RTQ|56
QFND498B
Orderable Information
slvsce7a_oa
slvsce7a_pm
9 Parameter Measurement Information
9.1 Pin Equivalent Input and Output Schematic Diagrams
Figure 11. SIN, SCLK
Figure 13. GCLK
(1) X=R or G or B, n=0~15
Figure 15. OUTR0/G0/B0 Through OUTR15/G15/B15
Figure 12. LAT
Figure 14. SOUT
9.1.1 Test Circuits
(1) CL includes measurement probe and jig capacitance.
(2) X=R or G or B, n=0~15
Figure 16. Rise Time and Fall Time Test Circuit for OUTXn
(1) X=R or G or B, n=0~15
Figure 18. Constant Current Test Circuit for OUTXn
(1) CL includes measurement probe and jig capacitance.
Figure 17. Rise Time and Fall Time Test Circuit for SOUT
9.2 Timing Diagrams
(1) Input pulse rise and fall time is 1~3ns
(2) 8 + 8 mode (SEL_PWM=0)
Figure 19. Timing Diagrams