SLVSG10D November   2021  – July 2022 TLC6984

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Independent and Stackable Mode
        1. 8.3.1.1 Independent Mode
        2. 8.3.1.2 Stackable Mode
      2. 8.3.2 Current Setting
        1. 8.3.2.1 Brightness Control (BC) Function
        2. 8.3.2.2 Color Brightness Control (CC) Function
        3. 8.3.2.3 Choosing BC/CC for a Different Application
      3. 8.3.3 Frequency Multiplier
      4. 8.3.4 Line Transitioning Sequence
      5. 8.3.5 Protections and Diagnostics
        1. 8.3.5.1 Thermal Shutdown Protection
        2. 8.3.5.2 IREF Resistor Short Protection
        3. 8.3.5.3 LED Open Load Detection and Removal
          1. 8.3.5.3.1 LED Open Detection
          2. 8.3.5.3.2 Read LED Open Information
          3. 8.3.5.3.3 LED Open Caterpillar Removal
        4. 8.3.5.4 LED Short and Weak Short Circuitry Detection and Removal
          1. 8.3.5.4.1 LED Short and Weak Short Detection
          2. 8.3.5.4.2 Read LED Short Information
          3. 8.3.5.4.3 LSD Caterpillar Removal
    4. 8.4 Device Functional Modes
    5. 8.5 Continuous Clock Series Interface
      1. 8.5.1 Data Validity
      2. 8.5.2 CCSI Frame Format
      3. 8.5.3 Write Command
        1. 8.5.3.1 Chip Index Write Command
        2. 8.5.3.2 VSYNC Write Command
        3. 8.5.3.3 MPSM Write Command
        4. 8.5.3.4 Standby Clear and Enable Command
        5. 8.5.3.5 Soft_Reset Command
        6. 8.5.3.6 Data Write Command
      4. 8.5.4 Read Command
    6. 8.6 PWM Grayscale Control
      1. 8.6.1 Grayscale Data Storage and Display
        1. 8.6.1.1 Memory Structure Overview
        2. 8.6.1.2 Details of Memory Bank
        3. 8.6.1.3 Write a Frame Data into Memory Bank
      2. 8.6.2 PWM Control for Display
    7. 8.7 Register Maps
      1. 8.7.1  FC0
      2. 8.7.2  FC1
      3. 8.7.3  FC2
      4. 8.7.4  FC3
      5. 8.7.5  FC4
      6. 8.7.6  FC14
      7. 8.7.7  FC15
      8. 8.7.8  FC16
      9. 8.7.9  FC17
      10. 8.7.10 FC18
      11. 8.7.11 FC19
      12. 8.7.12 FC20
      13. 8.7.13 FC21
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 System Structure
        2. 9.2.1.2 SCLK Frequency
        3. 9.2.1.3 Internal GCLK Frequency
        4. 9.2.1.4 Line Switch Time
        5. 9.2.1.5 Blank Time Removal
        6. 9.2.1.6 BC and CC
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Chip Index Command
        2. 9.2.2.2 FC Registers Settings
        3. 9.2.2.3 Grayscale Data Write
        4. 9.2.2.4 VSYNC Command
        5. 9.2.2.5 LED Open and Short Read
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.7.3 FC2

FC2 is shown in Figure 8-31 and described in Table 8-9.

Figure 8-31 FC2 Register
47464544434241403938373635343332
MPSM_ENRESERVEDMOD_SIZESUBP_MAX_256CH_B_IMMUNITYCH_G_IMMUNITYCH_R_IMMUNITYRESERVEDLG_COLOR_B
R/W-0bR/W-0bR/W-111bR/W-0bR/W-1bR/W-1bR/W-1bR/W-000bR/W-0000b
31302928272625242322212019181716
LG_COLOR_GLG_COLOR_RDE_COUPLE1_BDE_COUPLE1_G
R/W-0000bR/W-0000bR/W-0000bR/W-0000b
1514131211109876543210
DE_COUPLE1_RV_PDC_BV_PDC_GV_PDC_R
R/W-0000bR/W-0110bR/W-0110bR/W-0110b
Table 8-9 FC2 Register Field Descriptions
BitFieldTypeResetDescription
3-0V_PDC_RR/W0110bSet the Red pre_discharge voltage (typical), the voltage value must not be higher than (VR-1.3 V).
0000b: 0.1 V
0001b: 0.2 V
0010b: 0.3 V
0011b: 0.4 V
0100b: 0.5 V
0101b: 0.6 V
0110b: 0.7 V
0111b: 0.8 V
1000b: 0.9 V
1001b: 1.0 V
1010b: 1.1 V
1011b: 1.3 V
1100b: 1.5 V
1101b: 1.7 V
1110b: 1.9 V
1111b: 2.1 V
7-4V_PDC_GR/W0110bSet the Green pre_discharge voltage (typical), the voltage value must not be higher than (VG-1.3V).
0000b: 0.1 V
0001b: 0.2 V
0010b: 0.3 V
0011b: 0.4 V
0100b: 0.5 V
0101b: 0.6 V
0110b: 0.7 V
0111b: 0.8 V
1000b: 0.9 V
1001b: 1.0 V
1010b: 1.1 V
1011b: 1.3 V
1100b: 1.5 V
1101b: 1.7 V
1110b: 1.9 V
1111b: 2.1 V
11-8V_PDC_BR/W0110bSet the Blue pre_discharge voltage (typical), the voltage value must not be higher than (VB-1.3V).
0000b: 0.1V
0001b: 0.2 V
0010b: 0.3 V
0011b: 0.4 V
0100b: 0.5 V
0101b: 0.6 V
0110b: 0.7 V
0111b: 0.8 V
1000b: 0.9 V
1001b: 1.0 V
1010b: 1.1 V
1011b: 1.3 V
1100b: 1.5 V
1101b: 1.7 V
1110b: 1.9 V
1111b: 2.1 V
15-12DE_COUPLE1_RR/W0000bSet the Red dummy rising one-shot level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
19-16DE_COUPLE1_GR/W0000bSet the Green dummy rising one-shot level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
23-20DE_COUPLE1_BR/W0000bSet the Blue dummy rising one-shot level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
27-24LG_COLOR_RR/W0000bSet the Red rising one-shot level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
31-28LG_COLOR_GR/W0000bSet the Green rising one-shot level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
35-32LG_COLOR_BR/W0000bSet the Blue rising one-shot level
0000b: level 1 (lowest)
...
0111b: level 8 (middle)
...
1111b: level 16(highest)
38-36RESERVEDR/W000b
39CH_R_IMMUNITYR/W1bSet the immunity of the Red channels group
0b: high immunity
1b: low immunity
40CH_G_IMMUNITYR/W1bSet the immunity of the Green channels group
0b: high immunity
1b: low immunity
41CH_B_IMMUNITYR/W1bSet the immunity of the Blue channels group
0b: high immunity
1b: low immunity
42SUBP_MAX_256R/W0bSet the maximum subperiod to 256.
0b: disable
1b: enable
45-43MOD_SIZER/W111bSet the module size.
000b: 16x16 RGB pixels
001b:32x32 RGB pixels
010b:48x48 RGB pixels with D3 reverse, and scan sequence D1, D2, D3
48x48 RGB pixels with D3 reverse, and scan sequence D1, D3, D2
100b:48x64 RGB pixels with D3, D4 reverse, and scan sequence D1, D2, D3
101b:48x64 RGB pixels with D3,D4 reverse, and scan sequence D1, D3, D2
110b:64x64 RGB pixels with D3, D4 reserve, and scan seqeunce D1, D2, D3, D4
111b:64x64 RGB pixels with D3, D4 reverse,and scan sequence D1, D4, D2, D3
46RESERVEDR/W0b
47MPSM_ENR/W0bEnable or disable matrix power saving mode.
0b: disable
1b: enable