SLLSFE4A May   2022  – December 2022 TLIN1431-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings, IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Power Supply Characteristics
    7. 6.7 Electrical Characteristics
    8. 6.8 AC Switching Characteristics
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Test Circuit: Diagrams and Waveforms
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  LIN (Local Interconnect Network) Bus
        1. 8.3.1.1 LIN Transmitter Characteristics
        2. 8.3.1.2 LIN Receiver Characteristics
          1. 8.3.1.2.1 Termination
      2. 8.3.2  TXD (Transmit Input and Output)
      3. 8.3.3  RXD (Receive Output)
      4. 8.3.4  WAKE (High Voltage Local Wake Up Input)
      5. 8.3.5  WDT or CLK (Pin Programmable Watchdog Delay Input or SPI Clock)
      6. 8.3.6  WDI or SDI (Watchdog Timer Input or SPI Serial Data In)
      7. 8.3.7  PIN or nCS (Pin Watchdog Select or SPI Chip Select)
      8. 8.3.8  LIMP (Limp Home Output – High Voltage Open Drain Output)
        1. 8.3.8.1 LIMP in Pin Control Mode
        2. 8.3.8.2 LIMP in SPI Control Mode
      9. 8.3.9  nWDR/SDO (Watchdog Timeout Reset Output/SPI Serial Data Out)
      10. 8.3.10 HSS (High-side Switch)
      11. 8.3.11 HSSC or FSO (High-side Switch Control or Function Output)
      12. 8.3.12 WKRQ or INH (Wake Request or Inhibit)
      13. 8.3.13 PV
      14. 8.3.14 DIV_ON
      15. 8.3.15 VBAT (Battery Voltage)
      16. 8.3.16 VSUP (Supply Voltage)
      17. 8.3.17 GND (Ground)
      18. 8.3.18 EN or nINT (Enable Input or Interrupt Output)
      19. 8.3.19 nRST (Reset Input and Reset Output)
      20. 8.3.20 VCC (Supply Output)
      21. 8.3.21 VBAT Voltage Divider
      22. 8.3.22 Protection Features
        1. 8.3.22.1  Sleep Wake Error (SWE) Timer
        2. 8.3.22.2  Device Reset
        3. 8.3.22.3  TXD Dominant Time Out (DTO)
        4. 8.3.22.4  Bus Stuck Dominant System Fault: False Wake Up Lockout
        5. 8.3.22.5  Thermal Shutdown
        6. 8.3.22.6  Under-voltage on VSUP
        7. 8.3.22.7  Unpowered Device and LIN Bus
        8. 8.3.22.8  Floating Pins
        9. 8.3.22.9  VCC Voltage Regulator
          1. 8.3.22.9.1 Under or Over Voltage and Short Circuit
          2. 8.3.22.9.2 Output Capacitance Selection
          3. 8.3.22.9.3 Low-Voltage Tracking
          4. 8.3.22.9.4 Power Supply Recommendation
        10. 8.3.22.10 Watchdog
          1. 8.3.22.10.1 Watchdog in Pin Control Mode
          2. 8.3.22.10.2 Watchdog in SPI Control Mode
          3. 8.3.22.10.3 Watchdog Error Counter
          4. 8.3.22.10.4 Pin Control Mode
          5. 8.3.22.10.5 SPI Control Programming
          6. 8.3.22.10.6 Watchdog Register Relationship
          7. 8.3.22.10.7 Watchdog Timing
      23. 8.3.23 Channel Expansion
        1. 8.3.23.1 Channel Expansion for LIN
        2. 8.3.23.2 Channel Expansion for CAN Transceiver
    4. 8.4 Device Functional Modes
      1. 8.4.1 Init Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Fast Mode
      4. 8.4.4 Sleep Mode
      5. 8.4.5 Standby Mode
      6. 8.4.6 Restart Mode
        1. 8.4.6.1 Restart Counter
        2. 8.4.6.2 nRST Behavior in Restart Mode
      7. 8.4.7 Fail-safe Mode
      8. 8.4.8 Wake Up Events
        1. 8.4.8.1 Wake Up Request (RXD)
        2. 8.4.8.2 Local Wake Up (LWU) via WAKE Terminal
          1. 8.4.8.2.1 Static WAKE
          2. 8.4.8.2.2 Cyclic Sense Wake
      9. 8.4.9 Mode Transitions
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 Cyclic Redundancy Check
        2. 8.5.1.2 Chip Select Not (nCS)
        3. 8.5.1.3 Serial Clock Input (CLK)
        4. 8.5.1.4 Serial Data Input (SDI)
        5. 8.5.1.5 Serial Data Output (SDO)
    6. 8.6 Registers
      1. 8.6.1  DEVICE_ID_y Register (Address = 0h + formula) [reset = 0h]
      2. 8.6.2  REV_ID_MAJOR Register (Address = 8h) [reset = 01h]
      3. 8.6.3  REV_ID_MINOR Register (Address = 9h) [reset = 0h]
      4. 8.6.4  CRC_CNTL Register (Address = Ah) [reset = 0h]
      5. 8.6.5  CRC_POLY_SET (Address = Bh) [reset = 00h]
      6. 8.6.6  Scratch_Pad_SPI Register (Address = Fh) [reset = 0h]
      7. 8.6.7  WAKE_PIN_CONFIG1 Register (Address = 11h) [reset = 04h]
      8. 8.6.8  WAKE_PIN_CONFIG2 Register (Address = 12h) [reset = 2h]
      9. 8.6.9  WD_CONFIG_1 Register (Address = 13h) [reset = 90h]
      10. 8.6.10 WD_CONFIG_2 Register (Address = 14h) [reset = 02h]
      11. 8.6.11 WD_INPUT_TRIG Register (Address = 15h) [reset = 0h]
      12. 8.6.12 WD_RST_PULSE Register (Address = 16h) [reset = 40h]
      13. 8.6.13 FSM_CONFIG Register (Address = 17h) [reset = 0h]
      14. 8.6.14 FSM_CNTR Register (Address = 18h) [reset = 0h]
      15. 8.6.15 DEVICE_RST Register (Address = 19h) [reset = 0h]
      16. 8.6.16 DEVICE_CONFIG (Address = 1Ah) [reset = 80h]
      17. 8.6.17 DEVICE_CONFIG2 (Address = 1Bh) [reset = 0h]
      18. 8.6.18 SWE_TIMER (Address = 1Ch) [reset = 30h]
      19. 8.6.19 LIN_CNTL (Address = 1Dh) [reset = 00h]
      20. 8.6.20 HSS_CNTL (Address = 1Eh) [reset = 0h]
      21. 8.6.21 PWM1_CNTL1 (Address = 1Fh) [reset = 0h]
      22. 8.6.22 PWM1_CNTL2 (Address = 20h) [reset = 0h]
      23. 8.6.23 PWM1_CNTL3 (Address = 21h) [reset = 00h]
      24. 8.6.24 PWM2_CNTL1 (Address = 22h) [reset = 0h]
      25. 8.6.25 PWM2_CNTL2 (Address = 23h) [reset = 0h]
      26. 8.6.26 PWM2_CNTL3 (Address = 24h) [reset = 0h]
      27. 8.6.27 TIMER1_CONFIG (Address = 25h) [reset = 00h]
      28. 8.6.28 TIMER2_CONFIG (Address = 26h) [reset = 00h]
      29. 8.6.29 RSRT_CNTR (Address = 28h) [reset = 40h]
      30. 8.6.30 nRST_CNTL (Address = 29h) [reset = 00h]
      31. 8.6.31 INT_GLOBAL Register (Address = 50h) [reset = A0h]
      32. 8.6.32 INT_1 Register (Address = 51h) [reset = 0h]
      33. 8.6.33 INT_2 Register (Address = 52h) [reset = 40h]
      34. 8.6.34 INT_3 Register (Address 53h) [reset = 0h]
      35. 8.6.35 INT_EN_1 Register (Address = 56h) [reset = B0h]
      36. 8.6.36 INT_EN_2 Register (Address = 57h) [reset = 37h]
      37. 8.6.37 INT_EN_3 Register (Address =58h) [reset = BCh]
      38. 8.6.38 INT_4 Register (Address = 5Ah) [reset = 0h]
      39. 8.6.39 INT_EN_4 Register (Address = 5Eh) [reset = CCh]
      40. 8.6.40 Reserved Registers
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Brownout Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Normal Mode Application Note
        2. 9.2.1.2 Standby Mode Application Note
        3. 9.2.1.3 TXD Dominant State Timeout Application Note
      2. 9.2.2 Detailed Design Procedures
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RXD Output Terminal
VOH High level output voltage IO = –2 mA, VCC = Active 0.8 VCC
VOL Low level output voltage IO = 2 mA, VCC = Active 0.2 VCC
ILKG(OFF) Unpowered leakage current Outputs = 5.25/3.465 V, VCC = VSUP = 0 V –1 1 µA
TXD Input Terminal
VIL Low level input voltage –0.3 0.8 V
VIH High level input voltage 2 5.5 V
IIH High level input leakage current TXD = VIH –5 0 5 µA
RTXD Internal pull-up resistor value 125 350 800 kΩ
LIN Terminal (Referenced to VSUP)
VOH HIGH level output voltage(5) LIN recessive, TXD = high, IO = 0 mA, VSUP = 5.5 V to 28 V 0.85 VSUP
VOL LOW level output voltage(5) LIN dominant, TXD = low, VSUP = 5.5 V to 28 V 0.2 VSUP
VSUP_NON_OP VSUP where impact of recessive LIN bus < 5% (ISO/DIS 17987 Param 11) TXD & RXD open VLIN = 5.5 V to 45 V –0.3 45 V
I BUS_LIM Limiting current (ISO/DIS 17987 Param 12) TXD = 0 V, VLIN = 28 V, RMEAS = 440 Ω, VSUP = 28 V,
VBUSdom ≤ 0.251 * VSUP
40 90 200 mA
I BUS_PAS_dom Receiver leakage current, dominant (ISO/DIS 17987 Param 13) VLIN = 0 V, VSUP = 12 V Driver off/recessive –1 mA
I BUS_PAS_rec1 Receiver leakage current, recessive (ISO/DIS 17987 Param 14) VLIN ≥ VSUP, 5.5 V ≤ VSUP ≤ 28 V Driver off 20 µA
I BUS_PAS_rec2 Receiver leakage current, recessive (ISO/DIS 17987 Param 14) VLIN = VSUP, Driver off –5 5 µA
I BUS_NO_GND Leakage current, loss of ground (ISO/DIS 17987 Param 15) GND = VSUP, VSUP = 12 V, 0 V ≤ VLIN ≤ 28 V –1 1 mA
IBUS_NO_BAT Leakage current, loss of supply (ISO/DIS 17987 Param 16) 0 V ≤ VLIN ≤ 28 V, VSUP = GND 10 µA
VBUSdom Low level input voltage (ISO/DIS 17987 Param 17) LIN dominant (including LIN dominant for wake up);  Figure 7-2 0.4 VSUP
VBUSrec High level input voltage (ISO/DIS 17987 Param 18) LIN recessive;  Figure 7-2 0.6 VSUP
VBUS_CNT Receiver center threshold (ISO/DIS 17987 Param 19) VBUS_CNT = (VIL + VIH)/2; Figure 7-2 0.475 0.5 0.525 VSUP
VHYS Hysteresis voltage (ISO/DIS 17987 Param 20)(6)(7) VHYS = (VIL - VIH);  Figure 7-2 0.175 VSUP
VSERIAL_DIODE Serial diode LIN term pull-up path (ISO/DIS 17987 Param 21) By design and characterization 0.4 0.7 1.0 V
RLIN Internal pull-up resistor to VSUP on LIN (ISO/DIS 17987 Param 26) Normal and Standby modes 20 45 60 kΩ
IRSLEEP Pull-up current source to VSUP Sleep mode, VSUP = 12 V, LIN = GND –20 –2 µA
CLIN,PIN Capacitance of the LIN pin By design and characterization 25 pF
EN Input Terminal
VIH High level input voltage 2 5.5 V
VIL Low level input voltage 0.8 V
VHYS Hysteresis voltage By design and characterization 30 500 mV
IIL Low level input current EN = Low –8 8 µA
REN Internal pull-down resistor 125 350 800 kΩ
LIMP Output Terminal (High Voltage Open-drain Output)
ΔVH Hi-level voltage drop for LIMP with respect to VSUP ILIMP = –60 mA 0.42 1.2 V
Rdson LIMP output drain-to-source on resistance IO = –60 mA 7 20
ILKG(LIMP) Leakage current LIMP = 0 V, Sleep Mode –1 1 µA
HSS, INH high voltage open drain output pin
VDET_INH Voltage on INH/WKRQ pin during tDET_INH time VSUP = 14V 1.5 V
ΔVHINH Hi-level voltage drop for INH with respect to VSUP IINH = –6 mA 0.5 1 V
ΔVHHSS Hi-level voltage drop for HSS with respect to VSUP IHSS = –60 mA 0.42 1.2 V
Rdson HSS output drain-to-source on resistance IO = –60 mA 7 17
IO(HSS) Output current support VSUP = 14 V, 60 100 mA
IOC(HSS) HSS overcurrent limit VSUP = 14 V 150 300 mA
IOL(HSS) HSS open load current VSUP = 14 V –2.5 mA
IOLHYS(HSS) HSS open load current hysteresis VSUP = 14 V 0.05 0.45 1 mA
Ilkg Leakage current INH, HSS = 0 V, Sleep Mode –1 1 µA
tR/F Output rise and fall times (HSS) 5.5 V ≤ VSUP ≤ 28 V, ILOAD = 60 mA, RL = 220 Ω,  80%/20% 0.6 2.5 V/µs
tHSS_on Switching on delay (HSS) from SPI command to on VSUP = 14 V, ILOAD = 60 mA, VOUT = 80% of VSUP 60 µs
tHSS_off Switching off delay (HSS) from SPI command to off VSUP = 14 V, ILOAD = 60 mA, VOUT = 20% of VSUP 140 µs
tOCFLTR HSS overcurrent filter time(2) VSUP = 14 V 16 µs
tOLFLTR HSS open load filter time(2) VSUP = 14 V 64 µs
tOCOFF HSS overcurrent shut off time IO(HSS) > IOC(HSS) 200 300 µs
WAKE Input Terminal
VIH High-level input voltage Sleep or Standby Mode, WAKE pin enabled 4 V
VIL Low-level input voltage Sleep or Standby Mode, WAKE pin enabled 2 V
IIL Low-level input leakage current WAKE = 1 V 15 25 µA
tWAKE Wake up hold time from a wake edge on WAKE in standby or sleep mode for static sensing.. See Figure 8-44 and Figure 8-45 140 µs
tWAKE_INVALID WAKE pin pulses shorter than this will be filtered out in standby or sleep mode for static and cyclic sensing. See Figure 8-44 and Figure 8-45 10 µs
WDI, SDI, CLK, nCS Input Terminal
VIH High-level input voltage 2.19 V
VIL Low-level input voltage 0.8 V
IIH High-level input leakage current Inputs = VCC –1 1 µA
IIL Low-level input leakage current Inputs = 0 V, VCC = Active –50 µA
CIN Input Capacitance 4 MHz 10 15 pF
ILKG(OFF) Unpowered leakage current Inputs = 5.25/3.465 V, VCC = VSUP = 0 V –1 1 µA
RWDI_SDIpu Internal pull-up resistor on WDI/SDI pin 100 240 400 kΩ
RCLKpu Internal pull-up resistor on WDT/CLK pin SPI control only for CLK 100 240 400 kΩ
RnCSpu Internal pull-up resistor on PIN/nCS pin SPI control only for nCS 100 240 400 kΩ
WDT Input Terminal
VIH High-level input voltage Inputs = VCC 0.8     VCC
VIL Low-level input voltage Inputs = VCC     0.2 VCC
VIM(WDT) WDT Mid-level input voltage(1) Inputs = VCC 0.4 0.5 0.6 VCC
IIH High-level input leakage current Inputs = VCC  2.5   25 µA
IIL Low-level input leakage current Inputs = 0 V, VCC = Active –25   –2.5 µA
ILKG(OFF) Unpowered leakage current Inputs = 5.25/3.465 V, VCC = VSUP = 0 V –3   3 µA
SDO Output Terminal
VOH High level output voltage IO = –2 mA, VCC = Active 0.8 VCC
VOL Low level output voltage IO = 2 mA, VCC = Active 0.2 VCC
ILKG(OFF) Unpowered leakage current Outputs = 5.25/3.465 V, VCC = VSUP = 0 V –1 1 µA
nRST Terminal; input/output reset (Open-drain)
ILKG Leakage current, high-level LIN = VSUP, nRST = VCC –5   5 µA
VOL Low-level output voltage Based upon external pull up to VCC     0.2 VCC
IOL Low-level output current, open drain LIN = 0 V, nRST = 0.4 V 1.5   mA
Vth(sw) Switching threshold voltage 0.25 0.75 VCC
RPU Pull-up resistance 30 45 65 kΩ
nINT, nWDR, WKRQ Terminal
VOH High level output voltage IO = –2 mA, VCC = Active 0.8 VCC
VOL Low-level output voltage IO = 2 mA, VCC = Active 0.2 VCC
ILKG(OFF) Unpowered leakage current (nINT and nWDR pins) Outputs = 5.25/3.465 V, VCC = VSUP = 0 V –1 1 µA
HSSC
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0.8 V
IIL Low-level input current VIN = 0 V –1 1 µA
RHSSC Pull-down resistor 150 350 800 kΩ
fSW Switching frequency VHSS = 14 V, IO(HSS) = 60 mA 400 Hz
WDI, WDT TIMING and SWITCHING CHARACTERISTIC (RL = 1 MΩ, CL = 50 pF and TJ = -40°C to 150°C)
tW WDI pulse width; see Figure 7-8 Filter time to avoid false input 30 µs
tWINDOW Closed Window + Open Window; See Figure 7-8 WDT = GND 32 40 48 ms
WDT = VCC 480 600 720 ms
WDT = Floating 4.8 6 7.2 s
DIV_ON
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0.8 V
IIL Low-level input current VDIV_ON = 0 V –1 1 µA
RDIV_ON Pull-down resistor 150 370 800 kΩ
PV
Ratio Divider ratio 5 V VCC VBAT = 5.5 V to 28 V 1:7
Ratio Divider ratio 3.3 V VCC VBAT = 5.5 V to 20 V 1:9
ERR Divider ratio error VBAT = 5.5 V to 28 V –2 2 %
VBATLIN5 Linear voltage range for VBAT for 5 V LDO (3) RLOAD = 470 Ω ± 5% and CLOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20%, 5.5 V ≤ VBAT ≤ 28 V 0.735 4.05 V
VBATLIN3 Linear voltage range for VBAT for 3.3 V LDO and when I/O is 3.3 V with 5 V LDO (4) RLOAD = 470 Ω ± 5% and CLOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20%, 5.5 V ≤ VBAT ≤ 20 V 0.561 2.27 V
VMAX5V Maximum VPVOUT 28 V < VBAT ≤ 42 V, 470 Ω ± 5% and CLOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20% 5.1 V
VMAX3.3V Maximum VPVOUT for 3.3 V LDO and when I/O is 3.3 V with 5 V LDO 20 V < VBAT ≤ 42 V, 470 Ω ± 5% and CLOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20% 3.36 V
VVCC5V_VIO3V Voltage when VCC = 5 V and I/O is at 3.3 V RLOAD = 470 Ω ± 5% and CLOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20% and I/O voltage is ≤ 3.6 V 3.36 V
CPIN Pin capacitance 12 pF
tSET Settling time of the buffer 470 Ω ± 5% and CLOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20% 50 µs
Duty Cycle Characteristics
D1 Duty Cycle 1 (ISO/DIS 17987 Param 27 and J2602 Normal battery)(8)(9) THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP,
VSUP = 7 V to 18 V, tBIT = 50/52 µs,
D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 7-3, Figure 7-4)
0.396
D2 Duty Cycle 2 (ISO/DIS 17987 Param 28 and J2602 Normal battery)(8)(9) THREC(MIN) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP, VSUP = 7.6 V to 18 V,
tBIT = 50/52 µs, D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 7-3, Figure 7-4)
0.581
D3 Duty Cycle 3 (ISO/DIS 17987 Param 29 and J2602 Normal battery)(8)(9) THREC(MAX) = 0.778 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 7.0 V to 18 V, tBIT = 96 µs, D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 7-3, Figure 7-4) 0.417
D4 Duty Cycle 4 (ISO/DIS 17987 Param 30 and J2602 Normal battery)(8)(9) THREC(MIN) = 0.389 x VSUP,
THDOM(MIN) = 0.251 x VSUP,
VSUP = 7.6 V to 18 V, tBIT = 96 µs,
D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 7-3, Figure 7-4)
0.59
D1LB Duty Cycle 1
J2602 Low battery(9)(10)
THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP, VSUP = 5.5 V to 7 V, tBIT = 50/52 µs, D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 7-3, Figure 7-4) 0.396
D2LB Duty Cycle 2
J2602 Lowl battery(9)(10)
THREC(MIN) = 0.496 x VSUP, THDOM(MIN) = 0.361 x VSUP, VSUP = 6.1 V to 7.6 V, tBIT = 50/52 µs, D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 7-3, Figure 7-4) 0.581
D3LB Duty Cycle 3
J2602 Low battery(9)(10)
THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP, VSUP = 5.5 V to 7 V, tBIT = 96 µs, D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 7-3, Figure 7-4) 0.417
D4LB Duty Cycle 4
J2602 Lowl battery(9)(10)
THREC(MIN) = 0.496 x VSUP, THDOM(MIN) = 0.361 x VSUP, VSUP = 6.1 V to 7.6 V, tBIT = 96 µs, D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 7-3, Figure 7-4) 0.59
This is the measured voltage at the WDT pin when left floating.  The WDT pin should be connected directly to VCC, GND or left floating.
Specified by design
VBATLIN5 = [(1/7) * VBAT] +/- 50 mV for the linear range of the PV buffer
VBATLIN3 = [(1/9) * VBAT] +/- 50 mV for the linear range of the PV buffer
SAE J2602 loads include: commander node: 5.5 nF; 4 kΩ and for a responder node: 5.5 nF; 875 Ω
VHYS is defined for both ISO 17987 and SAE J2602-1.
VHYS = (Vth_rec - Vth_dom) where Vth_rec  and Vth_dom are the actual voltage values from VBUSrec and VBUSdom
ISO 17987 loads include 1 nF; 1 kΩ/ 6.8nF; 660 Ω/ 10 nF; 500 Ω; with tBIT values of 50 µs and 96 µs
SAE J2602 loads include: commander node: 5.5 nF; 4 kΩ/ 899 pF; 20 kΩ and for a responder node: 5.5 nF; 875 Ω/ 899 pF; 900 Ω; with tBIT values of 52 µs and 96 µs
ISO 17987 does not have a low battery specification.  Using the ISO 17987 loads these low battery duty cycle parameters are covered for tBIT values of 50 µs and 96 µs