SNOSDJ3A May   2024  – July 2025 TLV1812-EP , TLV1822-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5.   Pin Configuration and Functions
  6. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Switching Characteristics
  7. 5 Typical Characteristics
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Inputs
        1. 6.4.1.1 TLV18x2-EP Rail-to-Rail Input
        2. 6.4.1.2 ESD Protection
        3. 6.4.1.3 Unused Inputs
      2. 6.4.2 Outputs
        1. 6.4.2.1 TLV1812-EP Push-Pull Output
        2. 6.4.2.2 TLV1822-EP Open-Drain Output
      3. 6.4.3 Power-On Reset (POR)
      4. 6.4.4 Hysteresis
  9. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Basic Comparator Definitions
        1. 7.1.1.1 Operation
        2. 7.1.1.2 Propagation Delay
        3. 7.1.1.3 Overdrive and Underdrive Voltage
      2. 7.1.2 Hysteresis
        1. 7.1.2.1 Inverting Comparator With Hysteresis
        2. 7.1.2.2 Non-Inverting Comparator With Hysteresis
        3. 7.1.2.3 Inverting and Non-Inverting Hysteresis using Open-Drain Output
    2. 7.2 Typical Applications
      1. 7.2.1 Window Comparator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Square-Wave Oscillator
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curve
      3. 7.2.3 Adjustable Pulse Width Generator
      4. 7.2.4 Time Delay Generator
      5. 7.2.5 Logic Level Shifter
      6. 7.2.6 One-Shot Multivibrator
      7. 7.2.7 Bi-Stable Multivibrator
      8. 7.2.8 Zero Crossing Detector
      9. 7.2.9 Pulse Slicer
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.4 Thermal Information

THERMAL METRIC(1) TLV18x2-EP UNIT
DDF (SOT-23)
8 PINS
RθJA Junction-to-ambient thermal resistance 170.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 90.3 °C/W
RθJB Junction-to-board thermal resistance 88.1 °C/W
ψJT Junction-to-top characterization parameter 7.5 °C/W
ψJB Junction-to-board characterization parameter 87.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance – °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics report.