SLAS354C September   2001  – September 2015 TLV2553

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  External Reference Specifications
    7. 6.7  Operating Characteristics
    8. 6.8  Timing Requirements: VREF+ = 5 V
    9. 6.9  Timing Requirements: VREF+ = 2.5 V
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog MUX
      2. 8.3.2 Reference
    4. 8.4 Device Functional Modes
      1. 8.4.1  Converter Operation
      2. 8.4.2  Data I/O Cycle
      3. 8.4.3  Sampling Cycle
      4. 8.4.4  Conversion Cycle
      5. 8.4.5  Power Up and Initialization
        1. 8.4.5.1 Example
      6. 8.4.6  Data Input
      7. 8.4.7  Data Input—Address/Command Bits
      8. 8.4.8  Data Output Length
      9. 8.4.9  LSB Out First
      10. 8.4.10 Bipolar Output Format
      11. 8.4.11 EOC Output
      12. 8.4.12 Chip-Select Input (CS)
      13. 8.4.13 Power-Down Features
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

  • All decoupling capacitors must be located as close as possible to the loads they are supplying.
  • TI recommends large copper fill areas or thick traces wherever possible to provide low inductance current paths between decoupling capacitors and their loads
  • Ensure that there are no vias or discontinuities in the forward or return current paths that can cause the current loop area and therefore the loop inductance to increase.
  • For high-frequency current paths routed across PCB layers, multiple vias can be placed close together (but not obstructing the current path) to lower inductance.

11.2 Layout Example

TLV2553 layout_ex_las579.gif Figure 43. Layout Example Schematic