SLAS784A March   2012  – September 2015 TLV320AIC3212

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics, SAR ADC
    6. 8.6  Electrical Characteristics, ADC
    7. 8.7  Electrical Characteristics, Bypass Outputs
    8. 8.8  Electrical Characteristics, Microphone Interface
    9. 8.9  Electrical Characteristics, Audio DAC Outputs
    10. 8.10 Electrical Characteristics, Class-D Outputs
    11. 8.11 Electrical Characteristics, Miscellaneous
    12. 8.12 Electrical Characteristics, Logic Levels
    13. 8.13 Audio Data Serial Interface Timing (I2S): I2S/LJF/RJF Timing in Master Mode
    14. 8.14 Audio Data Serial Interface Timing (I2S): I2S/LJF/RJF Timing in Slave Mode
    15. 8.15 Typical DSP Timing: DSP/Mono PCM Timing in Master Mode
    16. 8.16 Typical DSP Timing: DSP/Mono PCM Timing in Slave Mode
    17. 8.17 I2C Interface Timing
    18. 8.18 SPI Timing
    19. 8.19 Typical Characteristics
      1. 8.19.1 Audio ADC Performance
      2. 8.19.2 Audio DAC Performance
      3. 8.19.3 Class-D Driver Performance
      4. 8.19.4 MICBIAS Performance
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Device Connections
        1. 10.3.1.1 Digital Pins
        2. 10.3.1.2 Analog Pins
        3. 10.3.1.3 Multifunction Pins
      2. 10.3.2 Analog Audio I/O
        1. 10.3.2.1 Analog Low Power Bypass
        2. 10.3.2.2 Headphone Outputs
          1. 10.3.2.2.1 Using the Headphone Amplifier
          2. 10.3.2.2.2 Ground-Centered Headphone Amplifier Configuration
            1. 10.3.2.2.2.1 Circuit Topology
            2. 10.3.2.2.2.2 Charge Pump Setup and Operation
            3. 10.3.2.2.2.3 Output Power Optimization
            4. 10.3.2.2.2.4 Offset Correction and Start-Up
            5. 10.3.2.2.2.5 Ground-Centered Headphone Setup
              1. 10.3.2.2.2.5.1 High Audio Output Power, High Performance Setup
              2. 10.3.2.2.2.5.2 High Audio Output Power, Low Power Consumption Setup
              3. 10.3.2.2.2.5.3 Medium Audio Output Power, High Performance Setup
              4. 10.3.2.2.2.5.4 Lowest Power Consumption, Medium Audio Output Power Setup
          3. 10.3.2.2.3 Stereo Unipolar Configuration
            1. 10.3.2.2.3.1 Circuit Topology
            2. 10.3.2.2.3.2 Unipolar Turn-On Transient (Pop) Reduction
          4. 10.3.2.2.4 Mono Differential DAC to Mono Differential Headphone Output
        3. 10.3.2.3 Stereo Line Outputs
          1. 10.3.2.3.1 Line Out Amplifier Configurations
        4. 10.3.2.4 Differential Receiver Output
        5. 10.3.2.5 Stereo Class-D Speaker Outputs
      3. 10.3.3 ADC / Digital Microphone Interface
        1. 10.3.3.1 ADC Processing Blocks — Overview
          1. 10.3.3.1.1 ADC Processing Blocks
      4. 10.3.4 DAC
        1. 10.3.4.1 DAC Processing Blocks — Overview
          1. 10.3.4.1.1 DAC Processing Blocks
      5. 10.3.5 Device Power Consumption
      6. 10.3.6 Powertune
      7. 10.3.7 Clock Generation and PLL
      8. 10.3.8 Interfaces
        1. 10.3.8.1 Control Interfaces
          1. 10.3.8.1.1 I2C Control
          2. 10.3.8.1.2 SPI Control
        2. 10.3.8.2 Digital Audio Interfaces
      9. 10.3.9 Device Special Functions
    4. 10.4 Device Functional Modes
      1. 10.4.1 Recording Mode
      2. 10.4.2 Playback Mode
      3. 10.4.3 Analog Low Power Bypass Modes
    5. 10.5 Register Maps
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Charge Pump Flying and Holding Capacitor
        2. 11.2.2.2 Reference Filtering Capacitor
        3. 11.2.2.3 MICBIAS
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Examples
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Community Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Layout

13.1 Layout Guidelines

Each system design and PCB layout is unique. The layout should be carefully reviewed in the context of a specific PCB design. However, the following guidelines can optimize TLV320AIC3212 performance:

  • The decoupling capacitors for the power supplies should be placed close to the device terminals. Figure 33 shows the recommended decoupling capacitors for the TLV320AIC3212.
  • Place the flying capacitor between CPFCP and CPFCM near the device terminals, with minimal VIAS in the trace between the device terminals and the capacitor. Similarly, keep the decoupling capacitor on VNEG near the device terminal with minimal VIAS in the trace between the device terminal, capacitor, and PCB ground.
  • TLV320AIC3212 internal voltage references must be filtered using external capacitors. Place the filter capacitors on VREF_SAR and VREF_AUDIO near the device terminals for optimal performance.
  • For analog differential audio signals, the signals should be routed differentially on the PCB for better noise immunity. Avoid crossing of digital and analog signals to avoid undesirable crosstalk.
  • Analog, speaker and digital grounds should be separated to prevent possible digital noise from affecting the analog performance of the board.

13.2 Layout Examples

Figure 36, Figure 37, and Figure 38 show some recommendations that must be followed to ensure the best performance of the device. See the TLV320AIC3212EVM (SLAU435) for details.

TLV320AIC3212 Ground_Layer_II_slas784.gif Figure 36. Ground Layer
TLV320AIC3212 I_O_Layer_II_slas784.gif Figure 37. I/O Layer
TLV320AIC3212 Power_Layer_II_slas784.gif Figure 38. Power Layer