SLAS679A
December 2011 – September 2015
TLV320AIC3262
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Device Comparison Table
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics, SAR ADC
8.6
Electrical Characteristics, ADC
8.7
Electrical Characteristics, Bypass Outputs
8.8
Electrical Characteristics, Microphone Interface
8.9
Electrical Characteristics, Audio DAC Outputs
8.10
Electrical Characteristics, Class-D Outputs
8.11
Electrical Characteristics, Miscellaneous
8.12
Electrical Characteristics, Logic Levels
8.13
I2S/LJF/RJF Timing in Master Mode (see )
8.14
I2S/LJF/RJF Timing in Slave Mode (see )
8.15
DSP/Mono PCM Timing in Slave Mode (see )
8.16
I2C Interface Timing (see )
8.17
SPI Interface Timing
8.18
Dissipation Ratings
8.19
Typical Characteristics
8.19.1
Audio ADC Performance
8.19.2
Audio DAC Performance
8.19.3
Class-D Driver Performance
8.19.4
MICBIAS Performance
9
Parameter Measurement Information
10
Detailed Description
10.1
Overview
10.2
Functional Block Diagram
10.3
Feature Description
10.3.1
Digital Pins
10.3.2
Analog Pins
10.3.3
Multifunction Pins
10.3.4
Analog Audio I/O
10.3.4.1
Analog Low Power Bypass
10.3.4.2
ADC Bypass Using Mixer Amplifiers
10.3.4.3
Headphone Outputs
10.3.4.4
Using the Headphone Amplifier
10.3.4.5
Ground-Centered Headphone Amplifier Configuration
10.3.4.6
Circuit Topology
10.3.4.7
Charge Pump Set-Up and Operation
10.3.4.8
Output Power Optimization
10.3.4.9
Offset Correction and Start-Up
10.3.4.10
Ground-Centered Headphone Setup
10.3.4.10.1
High Audio Output Power, High Performance Setup
10.3.4.10.2
High Audio Output Power, Low Power Consumption Setup
10.3.4.10.3
Medium Audio Output Power, High Performance Setup
10.3.4.10.4
Lowest Power Consumption, Medium Audio Output Power Setup
10.3.4.11
Stereo Unipolar Configuration
10.3.4.11.1
Circuit Topology
10.3.4.11.2
Unipolar Turn-On Transient (Pop) Reduction
10.3.4.12
Mono Differential DAC to Mono Differential Headphone Output
10.3.4.13
Stereo Line Outputs
10.3.4.14
Line Out Amplifier Configurations
10.3.4.15
Differential Receiver Output
10.3.4.16
Stereo Class-D Speaker Outputs
10.3.5
ADC / Digital Microphone Interface
10.3.5.1
ADC Processing Blocks - Overview
10.3.5.1.1
ADC Processing Blocks
10.3.6
DAC
10.3.6.1
DAC Processing Blocks — Overview
10.3.6.1.1
DAC Processing Blocks
10.3.7
Powertune
10.3.8
Clock Generation and PLL
10.3.9
Interfaces
10.3.9.1
Control Interfaces
10.3.9.1.1
I2C Control
10.3.9.1.2
SPI Control
10.3.9.2
Digital Audio Interfaces
10.3.9.3
miniDSP
10.3.9.3.1
miniDSP
10.3.9.3.2
Software
10.3.9.4
Asynchronous Sample Rate Conversion (ASRC)
10.3.10
Device Special Functions
10.3.11
Device Power Consumption
10.3.12
Powertune
10.3.13
Clock Generation and PLL
10.3.14
Interfaces
10.3.14.1
Control Interfaces
10.3.14.2
I2C Control
10.3.14.3
SPI Control
10.3.14.4
Digital Audio Interfaces
10.3.15
miniDSP
10.3.16
Device Special Functions
10.4
Device Functional Modes
10.4.1
Recording Mode
10.4.2
Playback Mode
10.4.3
Analog Low Power Bypass Modes
10.5
Register Maps
11
Application and Implementation
11.1
Application Information
11.2
Typical Application
11.2.1
Design Requirements
11.2.2
Detailed Design Procedure
11.2.2.1
Charge Pump Flying and Holding Capacitor
11.2.2.2
Reference Filtering Capacitor
11.2.2.3
MICBIAS
11.2.3
Application Curves
12
Power Supply Recommendations
12.1
Device Power Consumption
13
Layout
13.1
Layout Guidelines
13.2
Layout Examples
14
Device and Documentation Support
14.1
Documentation Support
14.1.1
Related Documentation
14.2
Community Resources
14.3
Trademarks
14.4
Electrostatic Discharge Caution
14.5
Glossary
15
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
YZF|81
MXBG143B
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slas679a_oa
slas679a_pm