The latch pin for the TLV3603-Q1 holds the output state of the device when the voltage at the LE/HYS pin is a logic low. This is particularly useful when the output state is intended to remain unchanged. An important consideration of the latch functionality is the latch hold and setup times. Latch hold time is the minimum time required (after the latch pin is asserted) for properly latching the comparator output. Likewise, latch setup time is defined as the time that the input must be stable before the latch pin is asserted low. The figure below illustrates when the input can transition for a valid latch. Note that the typical setup time in the EC table is negative; this is due to the internal trace delays of the LE/HYS pin relative to the input pin trace delays. A small delay (tPL) in the output response is shown below when the TLV3603-Q1 exits a latched output stage.