SBOS783 September   2016 TLV171 , TLV2171 , TLV4171

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: TLV171
    5. 6.5 Thermal Information: TLV2171
    6. 6.6 Thermal Information: TLV4171
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Characteristics
      2. 7.3.2 Phase-Reversal Protection
      3. 7.3.3 Electrical Overstress
      4. 7.3.4 Capacitive Load and Stability
    4. 7.4 Device Functional Modes
      1. 7.4.1 Common-Mode Voltage Range
      2. 7.4.2 Overload Recovery
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI™ (Free Software Download)
        2. 11.1.1.2 DIP Adapter EVM
        3. 11.1.1.3 Universal Op Amp EVM
        4. 11.1.1.4 TI Precision Designs
        5. 11.1.1.5 WEBENCH Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range, unless otherwise noted.(1)
MIN MAX UNIT
Voltage Supply voltage, V+ to V− –20 20 V
Signal input pin (V−) − 0.5 (V+) + 0.5
Current Signal input pin –10 10 mA
Output short-circuit(2) Continuous
Temperature Operating, TA –55 150 °C
Junction, TJ 150
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage (V+ – V–) Single supply 2.7 36 V
Dual supply ±1.35 ±18
Specified temperature –40 +125 °C

6.4 Thermal Information: TLV171

THERMAL METRIC(1) TLV171 UNIT
D (SOIC) DBV (SOT-23)
8 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 149.5 245.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 97.9 133.9 °C/W
RθJB Junction-to-board thermal resistance 87.7 83.6 °C/W
ψJT Junction-to-top characterization parameter 35.5 18.2 °C/W
ψJB Junction-to-board characterization parameter 89.5 83.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Thermal Information: TLV2171

THERMAL METRIC(1) TLV2171 UNIT
D (SOIC) DGK (VSSOP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 134.3 175.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 72.1 74.9 °C/W
RθJB Junction-to-board thermal resistance 60.6 22.2 °C/W
ψJT Junction-to-top characterization parameter 18.2 1.6 °C/W
ψJB Junction-to-board characterization parameter 53.8 22.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.6 Thermal Information: TLV4171

THERMAL METRIC(1) TLV4171 UNIT
D (SOIC) PW (TSSOP)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 93.2 106.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 51.8 24.4 °C/W
RθJB Junction-to-board thermal resistance 49.4 59.3 °C/W
ψJT Junction-to-top characterization parameter 13.5 0.6 °C/W
ψJB Junction-to-board characterization parameter 42.2 54.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.7 Electrical Characteristics

at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage TA = 25°C 0.75 ±2.7 mV
TA = –40°C to +125°C ±3.0
dVOS/dT Input offset voltage drift TA = –40°C to +125°C 1 µV/°C
PSRR Input offset voltage vs power supply VS = 4 V to 36 V, TA = –40°C to +125°C 90 105 dB
INPUT BIAS CURRENT
IB Input bias current ±10 pA
IOS Input offset current ±4 pA
NOISE
Input voltage noise f = 0.1 Hz to 10 Hz 3 µVPP
en Input voltage noise density f = 100 Hz 27 nV/√Hz
f = 1 kHz 16
INPUT VOLTAGE
VCM Common-mode voltage range(1) (V–) – 0.1 (V+) – 2 V
CMRR Common-mode rejection ratio VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C		 94 105 dB
INPUT IMPEDANCE
Differential 100 || 3 MΩ || pF
Common-mode 6 || 3 1012 Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 36 V,
(V–) + 0.35 V < VO < (V+) – 0.35 V,
TA = –40°C to +125°C		 94 130 dB
FREQUENCY RESPONSE
GBP Gain bandwidth product 3.0 MHz
SR Slew rate G = +1 1.5 V/µs
tS Settling time To 0.1%, VS = ±18 V, G = +1, 10-V step 6 µs
To 0.01% (12 bits), VS = ±18 V, G = +1,
10-V step		 10
Overload recovery time VIN × gain > VS 2 µs
THD+N Total harmonic distortion + noise G = +1, f = 1 kHz, VO = 3 VRMS 0.0002%
OUTPUT
VO Voltage output swing Positive rail, VS = ±18 V, RL = 10 kΩ,
TA = 25°C		 160 mV
Negative rail, VS = ±18 V, RL = 10 kΩ,
TA = 25°C		 90 mV
RL = 10 kΩ, AOL ≥ 94 dB,
TA = –40°C to +125°C		 (V–) + 0.35 (V+) – 0.35 V
ISC Short-circuit current 25 mA
–35
CLOAD Capacitive load drive See Typical Characteristics pF
RO Open-loop output resistance f = 1 MHz, IO = 0 A 150 Ω
POWER SUPPLY
VS Specified voltage range 2.7 36 V
IQ Quiescent current per amplifier IO = 0 A, TA = –40°C to +125°C 525 695 µA
TEMPERATURE
Specified range –40 125 °C
Operating range –55 150 °C
(1) The input range can be extended beyond (V+) – 2 V up to V+. See the Typical Characteristics and Application and Implementation sections for additional information.

6.8 Typical Characteristics

at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)

Table 1. Characteristic Performance Measurements

DESCRIPTION FIGURE
Offset Voltage Production Distribution Figure 1
Offset Voltage vs Common-Mode Voltage Figure 2
Offset Voltage vs Common-Mode Voltage (Upper Stage) Figure 3
Input Bias Current and Input Offset Current vs Temperature Figure 4
Output Voltage Swing vs Output Current (Maximum Supply) Figure 5
CMRR and PSRR vs Frequency (Referred-to-Input) Figure 6
0.1-Hz to 10-Hz Noise Figure 7
Input Voltage Noise Spectral Density vs Frequency Figure 8
Quiescent Current vs Supply Voltage Figure 9
Open-Loop Gain and Phase vs Frequency Figure 10
Closed-Loop Gain vs Frequency Figure 11
Open-Loop Gain vs Temperature Figure 12
Open-Loop Output Impedance vs Frequency Figure 13
Small-Signal Overshoot vs Capacitive Load Figure 14, Figure 15
No Phase Reversal Figure 16
Small-Signal Step Response (100 mV) Figure 17, Figure 18
Large-Signal Step Response Figure 19, Figure 20
Large-Signal Settling Time (10-V Positive Step) Figure 21
Large-Signal Settling Time (10-V Negative Step) Figure 22
Short-Circuit Current vs Temperature Figure 23
Maximum Output Voltage vs Frequency Figure 24
EMIRR IN+ vs Frequency Figure 25
TLV171 TLV2171 TLV4171 tc_histo_voff_sbos783.gif
Distribution taken from 3500 amplifiers
Figure 1. Offset Voltage Production Distribution
TLV171 TLV2171 TLV4171 tc_vos-vcm_upper_sbos783.gif
10 typical units shown
Figure 3. Offset Voltage vs Common-Mode Voltage
(Upper Stage)
TLV171 TLV2171 TLV4171 tc_vo_swing-io_bos516.gif
Figure 5. Output Voltage Swing vs Output Current (Maximum Supply)
TLV171 TLV2171 TLV4171 tc_noise_bos516.gif
Figure 7. 0.1-Hz to 10-Hz Noise
TLV171 TLV2171 TLV4171 tc_iq-vs_bos516.gif
Figure 9. Quiescent Current vs Supply Voltage
TLV171 TLV2171 TLV4171 tc_cloop_g-frq_bos516.gif
Figure 11. Closed-Loop Gain vs Frequency
TLV171 TLV2171 TLV4171 tc_oloop_imp-frq_bos516.gif
Figure 13. Open-Loop Output Impedance vs Frequency
TLV171 TLV2171 TLV4171 tc_small-sig_ovrst_cap_load_g-1_sbos783.gif
100-mV output step, RL = 10 kΩ
Figure 15. Small-Signal Overshoot vs Capacitive Load
TLV171 TLV2171 TLV4171 tc_sm_step_pos_sbos783.gif
RL = 10 kΩ, CL = 100 pF
Figure 17. Small-Signal Step Response (100 mV)
TLV171 TLV2171 TLV4171 tc_sm_step_pos_sbos783.gif
G = +1, RL = 10 kΩ, CL = 100 pF
Figure 19. Large-Signal Step Response
TLV171 TLV2171 TLV4171 tc_lg_t_pos_sbos783.gif
10-V positive step, G = –1
Figure 21. Large-Signal Settling Time
TLV171 TLV2171 TLV4171 tc_isc-tmp_bos516.gif
Figure 23. Short-Circuit Current vs Temperature
TLV171 TLV2171 TLV4171 D001_SBOS783.gif
Figure 25. EMIRR IN+ vs Frequency
TLV171 TLV2171 TLV4171 tc_vos-vcm_sbos783.gif
10 typical units shown
Figure 2. Offset Voltage vs Common-Mode Voltage
TLV171 TLV2171 TLV4171 tc_ibias-tmp_bos516.gif
Figure 4. Input Bias Current and Input Offset Current vs Temperature
TLV171 TLV2171 TLV4171 tc_cmrr_psrr-frq_bos516.gif
Figure 6. CMRR and PSRR vs Frequency
(Referred-to Input)
TLV171 TLV2171 TLV4171 tc_noise_spec-frq_bos516.gif
Figure 8. Input Voltage Noise Spectral Density vs Frequency
TLV171 TLV2171 TLV4171 tc_g_ph-frq_bos516.gif
Figure 10. Open-Loop Gain and Phase vs Frequency
TLV171 TLV2171 TLV4171 tc_g-tmp_sbos783.gif
5 typical units shown
Figure 12. Open-Loop Gain vs Temperature
TLV171 TLV2171 TLV4171 tc_small-sig_ovrst_cap_load_g1_sbos783.gif
100-mV output step, RL = 10 kΩ
Figure 14. Small-Signal Overshoot vs Capacitive Load
TLV171 TLV2171 TLV4171 tc_no_phase_reverse_bos782.gif
Figure 16. No Phase Reversal
TLV171 TLV2171 TLV4171 tc_sm_step_neg_sbos783.gif
Figure 18. Small-Signal Step Response (100 mV)
TLV171 TLV2171 TLV4171 tc_lg_step_neg_sbos783.gif
G = –1, RL = 10 kΩ, CL = 100 pF
Figure 20. Large-Signal Step Response
TLV171 TLV2171 TLV4171 tc_lg_t_neg_sbos783.gif
10-V negative step, G = –1
Figure 22. Large-Signal Settling Time
TLV171 TLV2171 TLV4171 tc_max_vo-frq_bos516.gif
Figure 24. Maximum Output Voltage vs Frequency