SBOS755 October   2016 TLV2376 , TLV376 , TLV4376

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: TLV376
    5. 6.5 Thermal Information: TLV2376
    6. 6.6 Thermal Information: TLV4376
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Capacitive Load and Stability
      3. 7.3.3 Input Offset Voltage and Input Offset Voltage Drift
      4. 7.3.4 Common-Mode Voltage Range
      5. 7.3.5 Input and ESD Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Operating Characteristics
      2. 8.1.2 Basic Amplifier Configurations
      3. 8.1.3 Active Filtering
      4. 8.1.4 Driving an Analog-to-Digital Converter
      5. 8.1.5 Phantom-Powered Microphone
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI (Free Software Download)
        2. 11.1.1.2 TI Precision Designs
        3. 11.1.1.3 WEBENCH® Filter Designer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage Supply, VS = (V+) – (V–) 7 V
Signal input pin(2) (V–) – 0.5 (V+) + 0.5 V
Current Signal input pin(2) –10 10 mA
Output short-circuit(3) Continuous
Temperature Specified, TA –40 125 °C
Junction, TJ 150
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage, VS = (V+) – (V–) Single supply 2.2 5.5 V
Dual supply ±1.1 ±2.75
TA Specified temperature range –40 125 °C

6.4 Thermal Information: TLV376

THERMAL METRIC(1) TLV376 UNIT
D (SOIC) DBV (SOT-23)
8 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 100.1 273.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 42.4 126.8 °C/W
RθJB Junction-to-board thermal resistance 41.0 85.9 °C/W
ψJT Junction-to-top characterization parameter 4.8 10.9 °C/W
ψJB Junction-to-board characterization parameter 40.3 84.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Thermal Information: TLV2376

THERMAL METRIC(1) TLV2376 UNIT
D (SOIC) DGK (VSSOP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 111.1 171.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 54.7 63.9 °C/W
RθJB Junction-to-board thermal resistance 51.7 92.8 °C/W
ψJT Junction-to-top characterization parameter 10.5 9.2 °C/W
ψJB Junction-to-board characterization parameter 51.2 91.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.6 Thermal Information: TLV4376

THERMAL METRIC(1) TLV4376 UNIT
PW (TSSOP)
14 PINS
RθJA Junction-to-ambient thermal resistance 107.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 29.6 °C/W
RθJB Junction-to-board thermal resistance 52.6 °C/W
ψJT Junction-to-top characterization parameter 1.5 °C/W
ψJB Junction-to-board characterization parameter 51.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W

6.7 Electrical Characteristics

at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage TLV376, TLV2376 40 100 µV
TLV4376 50 125
dVOS/dT Offset voltage vs temperature TA = –40°C to +125°C 1.0 μV/°C
PSRR Power-supply rejection ratio VS = 2.2 V to 5.5 V, VCM < (V+) – 1.3 V 84 110 dB
Channel separation, dc TLV2376, TLV4376 0.5 mV/V
INPUT BIAS CURRENT
IB Input bias current 0.3 pA
TA = –40°C to +125°C See Typical Characteristics
IOS Input offset current 0.2 pA
NOISE
Input voltage noise f = 0.1 Hz to 10 Hz 2.2 µVPP
en Input voltage noise density f = 1 kHz 8.0 nV/√Hz
in Input current noise f = 1 kHz 2 fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio (V–) < VCM < (V+) – 1.3 V 72 88 dB
INPUT CAPACITANCE
Differential 6.5 pF
Common-mode 13 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain 100 mV < VO < (V+) – 100 mV, RL = 2 kΩ 100 126 dB
FREQUENCY RESPONSE (CL = 100 pF, VS = 5.5 V)
GBW Gain-bandwidth product 5.5 MHz
SR Slew rate G = 1 2 V/µs
tS Settling time To 0.1%, 2-V step , G = 1 1.6 µs
To 0.01%, 2-V step , G = 1 2
Overload recovery time VIN  × gain > VS 0.33 μs
THD+N Total harmonic distortion + noise VO = 1 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ 0.0005%
OUTPUT
Voltage output swing from rail RL = 10 kΩ 10 20 mV
ISC Short-circuit current Sourcing 30 mA
Sinking –50
CLOAD Capacitive load drive See Typical Characteristics
RO Open-loop output impedance 150 Ω
POWER SUPPLY
VS Specified voltage range 2.2 5.5 V
Operating voltage range 2 to 5.5 V
IQ Quiescent current per amplifier IO = 0 mA, VS = 5.5 V, VCM < (V+) – 1.3 V 815 1200 μA
TEMPERATURE
Specified range –40 125 °C

6.8 Typical Characteristics

at TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
TLV376 TLV2376 TLV4376 tc_open_gp-freq_bos406.gif
Figure 1. Open-Loop Gain and Phase vs Frequency
TLV376 TLV2376 TLV4376 tc_open_psrr-tmp_sbos755.gif
Figure 3. Open-Loop Gain and Power-Supply Rejection Ratio vs Temperature
TLV376 TLV2376 TLV4376 tc_v_noise_bos406.gif
Figure 5. Input Voltage Noise Spectral Density
TLV376 TLV2376 TLV4376 tc_cmrr-tmp_bos406.gif
Figure 7. Common-Mode Rejection Ratio vs Temperature
TLV376 TLV2376 TLV4376 tc_iq_cur-sv_sbos755.gif
Figure 9. Quiescent and Short-Circuit Current vs
Supply Voltage
TLV376 TLV2376 TLV4376 tc_ibc-tmp_bos406.gif
Figure 11. Input Bias Current vs Temperature
TLV376 TLV2376 TLV4376 tc_offset_vltg_sbos799.gif
Figure 13. Offset Voltage Production Distribution Histogram
TLV376 TLV2376 TLV4376 tc_max_out-frq_sbos755.gif
Figure 15. Maximum Output Voltage vs Frequency
TLV376 TLV2376 TLV4376 tc_resp_sm_sbos755.gif
G = +1 V/V, RL = 10 kΩ, CL = 50 pF
Figure 17. Small-Signal Pulse Response
TLV376 TLV2376 TLV4376 tc_set_tim-closed_bos406.gif
Figure 19. Settling Time vs Closed-Loop Gain
TLV376 TLV2376 TLV4376 tc_oloop_ro-frq_sbos755.gif
Figure 21. Open-Loop Output Resistance vs Frequency
TLV376 TLV2376 TLV4376 tc_ps-cmrr-freq_sbos755.gif
Figure 2. Power-Supply and Common-Mode Rejection Ratio vs Frequency
TLV376 TLV2376 TLV4376 tc_input_vr_sbos755.gif
Figure 4. 0.1-Hz to 10-Hz Input Voltage Noise
TLV376 TLV2376 TLV4376 tc_hd-freq_sbos755.gif
VS = 5 V, VCM = 2 V, VOUT = 1 VRMS
Figure 6. Total Harmonic Distortion + Noise vs Frequency
TLV376 TLV2376 TLV4376 tc_iq-tmp_bos406.gif
Figure 8. Quiescent Current vs Temperature
TLV376 TLV2376 TLV4376 tc_short_cir-tmp_sbos755.gif
VS = ±2.75 V
Figure 10. Short-Circuit Current vs Temperature
TLV376 TLV2376 TLV4376 tc_outv_outc_sbos755.gif
VS = ±2.75 V
Figure 12. Output Voltage vs Output Current
TLV376 TLV2376 TLV4376 tc_offset_vltg_drift_sbos755.gif
Figure 14. Offset Voltage Drift Production Distribution Histogram (–40°C to 125°C)
TLV376 TLV2376 TLV4376 tc_ss-load_cap_sbos755.gif
Figure 16. Small-Signal Overshoot vs Load Capacitance
TLV376 TLV2376 TLV4376 tc_resp_lg_sbos755.gif
G = +1 V/V, RL = 2 kΩ, CL = 50 pF
Figure 18. Large-Signal Pulse Response
TLV376 TLV2376 TLV4376 tc_ch_sep-frq_bos406.gif
Figure 20. Channel Separation vs Frequency