SLVSAK9H October   2011  – January 2017 TLV62080 , TLV62084 , TLV62084A


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 100% Duty-Cycle Low-Dropout Operation
      2. 8.3.2 Enabling and Disabling the Device
      3. 8.3.3 Output Discharge
      4. 8.3.4 Soft Start
      5. 8.3.5 Power Good
      6. 8.3.6 Undervoltage Lockout
      7. 8.3.7 Thermal Shutdown
      8. 8.3.8 Inductor Current-Limit
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Save Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Custom Design With WEBENCH® Tools
        2. Output Filter Design
        3. Inductor Selection
        4. Capacitor Selection
        5. Setting the Output Voltage
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
    3. 12.3 Related Links
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Receiving Notification of Documentation Updates
    7. 12.7 Community Resources
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description


The TLV62080 and TLV62084x synchronous switched-mode converters are based on DCS-Control™. DCS-Control™ is an advanced regulation topology that combines the advantages of hysteretic and voltage mode control.

The DCS-Control™ topology operates in PWM (pulse width modulation) mode for medium to heavy load conditions and in power save mode at light load currents. In PWM mode, the TLV6208x converter operates with the nominal switching frequency of 2 MHz, having a controlled frequency variation over the input voltage range. As the load current decreases, the converter enters power save mode, reducing the switching frequency and minimizing the IC quiescent current to achieve high efficiency over the entire load current range. DCS-Control™ supports both operation modes (PWM and PFM) using a single building block with a seamless transition from PWM to power save mode without effects on the output voltage. The TLV62080 and TLV62084x devices offer both excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits.

Functional Block Diagram


TLV62080 TLV62084 TLV62084A SLVSAK9_FBD.gif


Feature Description

100% Duty-Cycle Low-Dropout Operation

The devices offer low input-to-output voltage difference by entering the 100% duty-cycle mode. In this mode the high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. This mode is particularly useful in battery powered applications to achieve the longest operation time by taking full advantage of the whole battery voltage range. Equation 1 calculates the minimum input voltage to maintain regulation based on the load current and output voltage.


Equation 1. TLV62080 TLV62084 TLV62084A Eq_VIN_min_lvsae8.gif


  • VIN,MIN = Minimum input voltage
  • IOUT,MAX = Maximum output current
  • RDS(on) = High-side FET on-resistance
  • RL = Inductor ohmic resistance


Enabling and Disabling the Device

The device is enabled by setting the EN input to a logic HIGH. Accordingly, a logic LOW disables the device. If the device is enabled, the internal power stage starts switching and regulates the output voltage to the programmed threshold. The EN input must be terminated and not left floating.

Output Discharge

The output gets discharged through the SW terminal with a typical discharge resistor of RDIS whenever the device shuts down (by disable, thermal shutdown or UVLO).

Soft Start

When EN is set to start device operation, the device starts switching after a delay of about 40 μs and VOUT rises with a slope of about 10mV/μs (See Figure 16 and Figure 17 for typical startup operation). Soft start avoids excessive inrush current and creates a smooth output voltage rise slope. Soft start also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal impedance.

If the output voltage is not reached within the soft start time, such as in the case of heavy load, the converter enters standard operation. Consequently, the inductor current limit operates as described in Inductor Current-Limit. The TLV62080 and TLV62084x devices are able to start into a pre-biased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to the nominal value.

Power Good

The TLV62080 and TLV62084x devices have a power-good output going low when the output voltage is below the nominal value. The power good maintains high impedance once the output is above 95% of the regulated voltage, and is driven to low once the output voltage falls below typically 90% of the regulated voltage. The PG terminal is an open drain output and is specified to sink typically up to 0.5 mA. The power good output requires a pull-up resistor which is recommended connecting to the device output. When the device is off because of disable, UVLO, or thermal shutdown, the PG terminal is at high impedance. TLV62084A features PG=Low in these cases. Table 2 and Table 3 show the different PG operation for the TLV6208x and TLV62084A. The PG output can be left floating if unused.


Table 2. Power Good Pin Logic Table (TLV62080/84)

Device Information PG Logic Status
High Z Low
Enable (EN=High) VFB ≥ VPG
Shutdown (EN=Low)
Thermal Shutdown TJ > TJSD
Power Supply Removal VIN < 0.7V


Table 3. Power Good Pin Logic Table (TLV62084A)

Device Information PG Logic Status
High Z Low
Enable (EN=High) VFB ≥ VPG
Shutdown (EN=Low)
Thermal Shutdown TJ > TJSD
Power Supply Removal VIN < 0.7V


The PG signal can be used for sequencing of multiple rails by connecting to the EN terminal of other converters. Leave the PG terminal unconnected when not in use.

Undervoltage Lockout

To avoid misoperation of the device at low input voltages, an undervoltage lockout is implemented which shuts down the device at voltages lower than VUVLO with a VHYS_UVLO hysteresis.

Thermal Shutdown

The device goes into thermal shutdown once the junction temperature exceeds typically TJSD. Once the device temperature falls below the threshold, the device returns to normal operation automatically.

Inductor Current-Limit

The Inductor current-limit prevents the device from high inductor current and drawing excessive current from the battery or input voltage rail. Excessive current can occur with a shorted or saturated inductor, a heavy load, or shorted output circuit condition.

The incorporated inductor peak-current limit measures the current during the high-side and low-side power MOSFET on-phase. Once the high-side switch current-limit is tripped, the high-side MOSFET is turned off and the low-side MOSFET is turned on to reduce the inductor current. When the inductor current drops down to the low-side switch current-limit, the low-side MOSFET is turned off and the high-side switch is turned on again. This operation repeats until the inductor current does not reach the high-side switch current-limit. Because of an internal propagation delay, the real current-limit value exceeds the static-current limit in the Electrical Characteristics table.

Device Functional Modes

Power Save Mode

As the load current decreases, the TLV62080 and TLV62084x devices enter power save mode operation. During power save mode, the converter operates with a reduced switching frequency in PFM mode and with a minimum quiescent current maintaining high efficiency. Power save mode occurs when the inductor current becomes discontinuous. Operation in power save mode is based on a fixed on time architecture. The typical on time is given by ton = 400 ns × (VOUT / VIN). The switching frequency over the whole load current range is shown in Figure 8.