SLVSBC1D October   2013  – October 2016 TLV62565 , TLV62566


  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Power Save Mode
      2. 9.3.2 Enabling/Disabling the Device
      3. 9.3.3 Soft Start
      4. 9.3.4 Switch Current Limit
      5. 9.3.5 Power Good
    4. 9.4 Device Functional Modes
      1. 9.4.1 Under Voltage Lockout
      2. 9.4.2 Thermal Shutdown
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. Output Filter Design
        2. Inductor Selection
        3. Input and Output Capacitor Selection
      2. 10.2.2 Detailed Design Procedure
        1. Setting the Output Voltage
        2. Loop Stability
      3. 10.2.3 Application Performance Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Community Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

The TLV62565/6 device family includes two high-efficiency synchronous step-down converters. Each device operates with an adaptive on-time control scheme, which is able to dynamically adjust the on-time duration based on the input voltage and output voltage so that it can achieve relative constant frequency operation. The device operates at typically 1.5-MHz frequency pulse width modulation (PWM) at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit sets the required on time for the high-side MOSFET. It makes the switching frequency relatively constant regardless of the variation of input voltage, output voltage, and load current. At the beginning of each switching cycle, the high-side switch is turned on and the inductor current ramps up to a peak current that is defined by on time and inductance. In the second phase, once the on time expires, the high-side switch is turned off while the low-side switch is turned on. The current through the inductor then decays until triggering the valley current level determined by the output of the error amplifier. Once this occurs, the on timer is set to turn the high-side switch back on again and the cycle is repeated.

The TLV62565/6 device family offers excellent load transient response with a unique fast response constant on-time valley current mode. The switching frequency changes during load transition so that the output voltage comes back in regulation faster than a traditional fixed PWM control scheme. Internal loop compensation is integrated which simplifies the design process while minimizing the number of external components. At light load currents the device automatically operates in Power Save Mode with pulse frequency modulation (PFM).

9.2 Functional Block Diagrams

TLV62565 TLV62566 funct_block_tlv62565_adj_update.gif Figure 4. TLV62565 Functional Block Diagram
TLV62565 TLV62566 funct_block_tlv62566_adj.gif Figure 5. TLV62566 Functional Block Diagram

9.3 Feature Description

9.3.1 Power Save Mode

The device integrates a Power Save Mode with PFM to improve efficiency at light load, as shown in Figure 6

When the inductor current becomes discontinuous, the device enters Power Save Mode. In Power Save Mode, the FB voltage is typically 0.9% higher than the nominal value of 0.6 V. Thus the device ramps up the output voltage with several pulses, and the device stops switching when the output voltage reaches 0.9% above the nominal output voltage.

When the inductor current becomes continuous again, the device leaves Power Save Mode and the FB voltage is back to the norminal value of 0.6 V.

TLV62565 TLV62566 PFMPWM_TLV62565.gif Figure 6. Output Voltage in PFM/PWM Mode

9.3.2 Enabling/Disabling the Device

The TLV62565 is enabled by setting the EN input to a logic HIGH. Accordingly, a logic LOW disables the device. If the device is enabled, the internal power stage starts switching and regulates the output voltage to the set point voltage. The EN input must be terminated and should not be left floating.

9.3.3 Soft Start

After enabling the device, internal soft-start circuitry monotonically ramps up the output voltage which reaches nominal output voltage during a soft-start time of 250 µs (typical). This avoids excessive inrush current and creates a smooth output voltage rise slope. It also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal impedance.

If the output voltage is not reached within the soft-start time, such as in the case of a heavy load, the converter enters regular operation. The TLV62565/6 are able to start into a pre-biased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to its nominal value.

9.3.4 Switch Current Limit

The switch current limit prevents the device from high inductor current and drawing excessive current from a battery or input voltage rail. Excessive current might occur with a heavy load or shorted output circuit condition.

The TLV62565/6 adopt valley current control by sensing the current of the low-side FET. If the inductor current reaches the low-side FET valley current limit ILIM,LS (typical 1.7 A), the low-side FET is turned off and the high-side FET is turned on to ramp up the inductor current. The current ramping up time is controlled by the on time setting of the device, as shown in Figure 7. For example, the peak current is 1.97 A when the switch current limit is triggered with 3.6 VIN to 1.8 VOUT and 2.2-μH application.

To prevent the inductor current from running away, the devices implement an additional high-side peak current limit ILIM,HS (typical 2 A), which is shown in Figure 7. It forces to turn off the high side FET immediately once the peak inductor current reaches the threshold. Due to the internal propagation delay, the real current limit value might be higher than the static current limit in the electrical characteristics table.

TLV62565 TLV62566 Curr_Lim_TLV62565.gif Figure 7. Switch Current Limit

9.3.5 Power Good

The TLV62566 integrates a Power Good output going low when the output voltage is below its nominal value. The Power Good output stays high impedance once the output is above 95% of the regulated voltage and is low once the output voltage falls below typically 90% of the regulated voltage. The PG pin is an open drain output and is specified to sink typically up to 0.5 mA. The Power Good output requires a pull-up resistor connected to any voltage lower than 5.5 V. When the device is off due to UVLO or thermal shutdown, the PG pin is pulled to logic low.

9.4 Device Functional Modes

9.4.1 Under Voltage Lockout

To avoid mis-operation of the device at low input voltages, under voltage lockout is implemented that shuts down the device at voltages lower than VUVLO with VHYS_UVLO hysteresis.

9.4.2 Thermal Shutdown

The device enters thermal shutdown once the junction temperature exceeds typically TJSD. Once the device temperature falls below the threshold with hysteresis, the device returns to normal operation automatically. Power Good is pulled low when thermal protection is triggered.