SBVS305 March 2017 TLV703
The TLV703 series of low-dropout (LDO) linear regulators are low quiescent current devices with excellent line and load transient performance. These LDOs are designed for power-sensitive applications. A precision band-gap and error amplifier provides overall 2% accuracy. Low output noise, very high power-supply rejection ratio (PSRR), and low dropout voltage make this series of devices ideal for most battery-operated handheld equipment. All device versions have integrated thermal shutdown, current limit, and undervoltage lockout (UVLO).
The TLV703 internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the output voltage is not regulated, and is VOUT = ICL × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) × ICL until thermal shutdown is triggered and the device turns off. As the device cools, the internal thermal shutdown circuit turns the device back on. If the fault condition continues, the device cycles between current limit and thermal shutdown; see the Thermal Consideration section for more details.
The PMOS pass element in the TLV703 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended.
The enable pin (EN) is active high. The device is enabled when voltage at the EN pin goes above 0.9 V. The device is turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be connected to the IN pin.
The TLV703 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear (triode) region of operation and the input-to-output resistance is the RDS(on) of the PMOS pass element. VDO scales approximately with output current because the PMOS device functions as a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded when (VIN – VOUT) approaches dropout. Figure 12 illustrates this effect.
The TLV703 uses a UVLO circuit to keep the output shut off until internal circuitry is operating properly.
The device regulates to the nominal output voltage under the following conditions:
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this condition, the output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device is in a triode state and no longer regulates the output voltage of the LDO. Line or load transients in dropout can result in large output voltage deviations.
Table 1 lists the conditions that lead to the different modes of operation.
|Normal mode||VIN > VOUT (nom) + VDO||IOUT < ICL|
|Dropout mode||VIN < VOUT (nom) + VDO||IOUT < ICL|
|Current limit||VIN > UVLO||IOUT > ICL|