SLVSE84D December   2017  – July 2021

PRODUCTION DATA

1. Features
2. Applications
3. Description
4. Revision History
5. Pin Configuration and Functions
6. Specifications
7. Typical Characteristics
8. Detailed Description
1. 8.1 Overview
2. 8.2 Functional Block Diagrams
3. 8.3 Feature Description
4. 8.4 Device Functional Modes
9. Application and Implementation
1. 9.1 Application Information
2. 9.2 Typical Application
10. 10Power Supply Recommendations
11. 11Layout
12. 12Device and Documentation Support

• DRV|6
• DGN|8
• DBV|5
• DRV|6
• DGN|8

#### 9.2.2.2 Choose Feedback Resistors

For this design example, VOUT is set to 3.3 V. Equation 11 and Equation 12 set the feedback divider resistors for the desired output voltage:

Equation 11. VOUT = VFB × (1 + R1 / R2)
Equation 12. R1 + R2 ≤ VOUT / (IFB × 100)

For improved output accuracy, use Equation 12 and IFB = 50 nA as listed in the Electrical Characteristics table to calculate the upper limit for series feedback resistance (R1 + R2 ≤ 660 kΩ).

The control-loop error amplifier drives the FB pin to the same voltage as the internal reference (VFB = 0.8 V, as listed in the Electrical Characteristics table). Use Equation 11 to determine the ratio of R1 / R2 = 3.125. Use this ratio and solve Equation 12 for R2. Now calculate the upper limit for R2 ≤ 160 kΩ. Select a standard value resistor for R2 = 160 kΩ.

Reference Equation 11 and solve for R1:

Equation 13. R1 = (VOUT / VFB – 1) × R2

From Equation 13, R1 = 500 kΩ can be determined. Select a standard value resistor for R1 = 499 kΩ. VOUT = 3.3 V (as determined by Equation 11).