SBOSAD6A april   2023  – may 2023 TLV9361-Q1 , TLV9362-Q1 , TLV9364-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 EMI Rejection
      2. 7.3.2 Thermal Protection
      3. 7.3.3 Capacitive Load and Stability
      4. 7.3.4 Electrical Overstress
      5. 7.3.5 Overload Recovery
      6. 7.3.6 Typical Specifications and Distributions
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Low-Side Current Measurement
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 TINA-TI (Free Software Download)
        2. 9.1.1.2 TI Precision Designs
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Electrical Characteristics

For VS = (V+) – (V–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
OFFSET VOLTAGE
VOSInput offset voltageVCM = V–±0.4±1.7mV
TA = –40°C to 125°C±2
dVOS/dTInput offset voltage driftVCM = V–TA = –40°C to 125°C±1.25µV/℃
PSRRInput offset voltage versus power supplyVCM = V–, VS = 5 V to 40 V(1)TA = –40°C to 125°C±1.5±7.5μV/V
DC channel separation1µV/V
INPUT BIAS CURRENT
IBInput bias current±10pA
IOSInput offset current±10pA
NOISE
ENInput voltage noisef = 0.1 Hz to 10 Hz 6μVPP
 1 µVRMS
eNInput voltage noise densityf = 1 kHz8.5 nV/√Hz
f = 10 kHz 6 
iNInput current noise densityf = 1 kHz 100 fA/√Hz
INPUT VOLTAGE RANGE
VCMCommon-mode voltage range(V–)(V+) – 2V
CMRRCommon-mode rejection ratioVS = 40 V, V– < VCM < (V+) – 2 VTA = –40°C to 125°C95110dB
VS = 5 V, V– < VCM < (V+) – 2 V(1)7585
INPUT IMPEDANCE
ZIDDifferential100 || 9MΩ || pF
ZICMCommon-mode6 || 1TΩ || pF
OPEN-LOOP GAIN
AOLOpen-loop voltage gainVS = 40 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –  0.1 V		115130dB
VS = 40 V, VCM = VS / 2,
(V–) + 0.12 V < VO < (V+) –  0.12 V		TA = –40°C to 125°C130
VS = 5 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –  0.1 V(1)		100120
TA = –40°C to 125°C120
FREQUENCY RESPONSE
GBWGain-bandwidth product10.6MHz
SRSlew rateVS = 40 V, G = +1, VSTEP = 10 V, CL = 20 pF(3)25V/μs
tSSettling timeTo 0.1%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF0.65μs
To 0.1%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF0.3
To 0.01%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF0.86
To 0.01%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF0.44
Phase marginG = +1, RL = 10 kΩ, CL = 20 pF64°
Overload recovery timeVIN  × gain > VS170ns
THD+NTotal harmonic distortion + noiseVS = 40 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ0.0001%
120dB
VS = 10 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 128 Ω0.0056%
85dB
VS = 10 V, VO = 0.4 VRMS, G = 1, f = 1 kHz, RL = 32 Ω0.00056%
105dB
OUTPUT
 Voltage output swing from railPositive and negative
rail headroom		VS = 40 V, RL = no load 10mV
VS = 40 V, RL = 10 kΩ 60100
VS = 40 V, RL = 2 kΩ 250400
ISCShort-circuit current±60(2)mA
CLOADCapacitive Load DriveSee Figure 6-28pF
ZOOpen-loop output impedanceIO = 0 ASee Figure 6-25Ω
POWER SUPPLY
IQQuiescent current per amplifierIO = 0 A2.63mA
TA = –40°C to 125°C3.2
(1) Specified by characterization only.
(2) At high supply voltage, placing the TLV936x-Q1 in a sudden short to mid-supply or ground will lead to rapid thermal shutdown.  Output current greater than ISC can be achieved if rapid thermal shutdown is avoided as per Figure 6-12.
(3) See Figure 6-11 for more information.