SBOS473J March   2009  – February 2024 TMP112

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics (TMP112A/B/N)
    9. 6.9 Typical Characteristics (TMP112Dx)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Digital Temperature Output
      2. 7.3.2 Serial Interface
        1. 7.3.2.1 Bus Overview
        2. 7.3.2.2 Serial Bus Address
        3. 7.3.2.3 Writing and Reading Operation
        4. 7.3.2.4 Slave Mode Operations
          1. 7.3.2.4.1 Slave Receiver Mode
          2. 7.3.2.4.2 Slave Transmitter Mode
        5. 7.3.2.5 SMBus Alert Function
        6. 7.3.2.6 General Call
        7. 7.3.2.7 High-Speed (Hs) Mode
        8. 7.3.2.8 Timeout Function
        9. 7.3.2.9 Timing Diagrams
          1. 7.3.2.9.1 Two-Wire Timing Diagrams
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous-Conversion Mode
      2. 7.4.2 Extended Mode (EM)
      3. 7.4.3 One-Shot/Conversion Ready Mode (OS)
      4. 7.4.4 Thermostat Mode (TM)
        1. 7.4.4.1 Comparator Mode (TM = 0)
        2. 7.4.4.2 Interrupt Mode (TM = 1)
    5. 7.5 Programming
      1. 7.5.1 Pointer Register
      2. 7.5.2 Temperature Register
      3. 7.5.3 Configuration Register
        1. 7.5.3.1 Shutdown Mode (SD)
        2. 7.5.3.2 Thermostat Mode (TM)
        3. 7.5.3.3 Polarity (POL)
        4. 7.5.3.4 Fault Queue (F1/F0)
        5. 7.5.3.5 Converter Resolution (R1 and R0)
        6. 7.5.3.6 One-Shot (OS)
        7. 7.5.3.7 Extended Mode (EM)
        8. 7.5.3.8 Alert (AL)
      4. 7.5.4 High- and Low-Limit Register
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.4 High- and Low-Limit Register

The temperature limits are stored in the T(LOW) and T(HIGH) registers in the same format as the temperature result, and the values are compared to the temperature result on every conversion. The outcome of the comparison drives the behavior of the ALERT pin/flag, which operates as a comparator output or an interrupt, and is set by the TM bit in the configuration register.

In Comparator mode (TM = 0), the ALERT pin and status flag become active when the temperature equals or exceeds the value in the T(HIGH) register and generates a consecutive number of faults according to fault bits F1 and F0. The ALERT pin and status flag remain active until the temperature falls below the indicated T(LOW) value for the same number of faults.

In interrupt mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds the value in T(HIGH) for a consecutive number of fault conditions (as shown in Table 7-11). The ALERT pin remains active until a read operation of any register occurs, or the device successfully responds to the SMBus alert response address. The ALERT pin is also cleared if the device is placed in shutdown mode. When the ALERT pin is cleared, the pin becomes active again only when temperature falls below T(LOW), and remains active until cleared by a read operation of any register or a successful response to the SMBus alert response address. When the ALERT pin is cleared, the above cycle repeats, with the ALERT pin becoming active when the temperature equals or exceeds T(HIGH). The ALERT pin can also be cleared by resetting the device with the general-call Reset command. This action also clears the state of the internal registers in the device, returning the device to comparator mode (TM = 0).

Both operating modes are represented in Figure 7-9 and Figure 7-10. Table 7-12 and Table 7-13 list the format for the THIGH and TLOW registers. The most significant byte is sent first, followed by the least significant byte. The power-up reset values for T(HIGH) and T(LOW) are:

  • THIGH = +80°C
  • TLOW = +75°C

The format of the data for THIGH and TLOW is the same as for the Temperature Register.

Table 7-12 Bytes 1 and 2 of THIGH Register
BYTED7D6D5D4D3D2D1D0
1H11H10H9H8H7H6H5H4
(H12)(H11)(H10)(H9)(H8)(H7)(H6)(H5)
BYTED7D6D5D4D3D2D1D0
2H3H2H1H00000
(H4)(H3)(H2)(H1)(H0)(0)(0)(0)
Table 7-13 Bytes 1 and 2 of TLOW Register
BYTED7D6D5D4D3D2D1D0
1L11L10L9L8L7L6L5L4
(L12)(L11)(L10)(L9)(L8)(L7)(L6)(L5)
BYTED7D6D5D4D3D2D1D0
2L3L2L1L00000
(L4)(L3)(L2)(L1)(L0)(0)(0)(0)