SPRS591F Data sheet

SPRS591F November 2009 – January 2017 TMS320C6746

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

ZCE|361
ZWT|361

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6 Peripheral Information and Electrical Specifications

6.1 Parameter Information

6.1.1 Parameter Information Device-Specific Information

A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin and the input signals are driven between 0V and the appropriate IO supply rail for the signal.

Figure 6-1 Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

6.1.1.1 Signal Transition Levels

All input and output timing parameters are referenced to V_ref for both "0" and "1" logic levels.

For 3.3 V I/O, V_ref = 1.65 V.

For 1.8 V I/O, V_ref = 0.9 V.

For 1.2 V I/O, V_ref = 0.6 V.

Figure 6-2 Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to V_IL MAX and V_IH MIN for input clocks, V_OLMAX and V_OH MIN for output clocks

Figure 6-3 Rise and Fall Transition Time Voltage Reference Levels

6.2 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between V_IH and V_IL (or between V_IL and V_IH) in a monotonic manner.

6.3 Power Supplies

6.3.1 Power-On Sequence

The device should be powered-on in the following order:

RTC (RTC_CVDD) may be powered from an external device (such as a battery) prior to all other supplies being applied or powered-up at the same time as CVDD. If the RTC is not used, RTC_CVDD should be connected to CVDD. RTC_CVDD should not be left unpowered while CVDD is powered.
Core logic supplies:
1. All variable 1.3V - 1.0V core logic supplies (CVDD)
2. All static core logic supplies (RVDD, PLL0_VDDA, PLL1_VDDA, USB_CVDD). If voltage scaling is not used on the device, groups 2a) and 2b) can be controlled from the same power supply and powered up together.
All static 1.8V IO supplies (DVDD18, DDR_DVDD18, and USB0_VDDA18 ) and any of the LVCMOS IO supply groups used at 1.8V nominal (DVDD3318_A, DVDD3318_B, or DVDD3318_C).
LVCMOS IO supply groups used at 3.3V nominal (DVDD3318_A, DVDD3318_B, or DVDD3318_C).

There is no specific required voltage ramp rate for any of the supplies as long as the LVCMOS supplies operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed the STATIC 1.8V supplies by more than 2 volts.

RESET must be maintained active until all power supplies have reached their nominal values.

6.3.2 Power-Off Sequence

The power supplies can be powered-off in any order as long as LVCMOS supplies operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed static 1.8V supplies by more than 2 volts. There is no specific required voltage ramp down rate for any of the supplies (except as required to meet the above mentioned voltage condition).

6.4 Reset

6.4.1 Power-On Reset (POR)

A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal logic to its default state. All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence, and RTCK/GP8[0]. During reset, GP8[0] is configured as a reserved function, and its behavior is not deterministic; the user should be aware that this pin will drive a level, and fact may toggle, during reset. RESETOUT in an output for use by other controllers in the system that indicates the device is currently in reset.

While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and device's emulation logic in the reset state.

TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.

RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan instructions work correctly independent of current state of RESET. For maximum reliability, the device includes an internal pulldown on the TRST pin to ensure that TRST will always be asserted upon power up and the device's internal emulation logic will always be properly initialized.

JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type of JTAG controller, assert TRST to intialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations.

A summary of the effects of Power-On Reset is given below:

All internal logic (including emulation logic and the PLL logic) is reset to its default state
Internal memory is not maintained through a POR
RESETOUT goes active
All device pins go to a high-impedance state
The RTC peripheral is not reset during a POR. A software sequence is required to reset the RTC

CAUTION: A watchdog reset triggers a POR.

6.4.2 Warm Reset

A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low (TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their default state while leaving others unaltered. All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence, and RTCK/GP8[0]. During reset, GP8[0] is configured as a reserved function, and its behavior is not deterministic; the user should be aware that this pin will drive a level, and fact may toggle, during reset. RESETOUT is an output for use by other controllers in the system that indicates the device is currently in reset.

During an emulation, the emulator will maintain TRST high and hence only warm reset (not POR) is available during emulation debug and development.

A summary of the effects of Warm Reset is given below:

All internal logic (except for the emulation logic and the PLL logic) is reset to its default state
Internal memory is maintained through a warm reset
RESETOUT goes active
All device pins go to a high-impedance state
The RTC peripheral is not reset during a warm reset. A software sequence is required to reset the RTC

6.4.3 Reset Electrical Data Timings

Table 6-1 assumes testing over the recommended operating conditions.

Table 6-1 Reset Timing Requirements (⁽¹⁾, ⁽²⁾)

NO.			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
1	t_w(RSTL)	Pulse width, RESET/TRST low	100		100		100		ns
2	t_su(BPV-RSTH)	Setup time, boot pins valid before RESET/TRST high	20		20		20		ns
3	t_h(RSTH-BPV)	Hold time, boot pins valid after RESET/TRST high	20		20		20		ns
4	t_{d(RSTH-RESETOUTH)}	RESET high to RESETOUT high; Warm reset	4096		4096		4096		cycles⁽³⁾
4	t_{d(RSTH-RESETOUTH)}	RESET high to RESETOUT high; Power-on Reset	6169		6169		6169		cycles⁽³⁾
5	t_{d(RSTL-RESETOUTL)}	Delay time, RESET/TRST low to RESETOUT low		14		16		20	ns

(1) RESETOUT is multiplexed with other pin functions. See the Terminal Functions table, Table 3-5 for details.

(2) For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this table refer to RESET only (TRST is held high).

(3) OSCIN cycles.

Figure 6-4 Power-On Reset (RESET and TRST active) Timing

Figure 6-5 Warm Reset (RESET active, TRST high) Timing

6.5 Crystal Oscillator or External Clock Input

The device includes two choices to provide an external clock input, which is fed to the on-chip PLLs to generate

high-frequency system clocks. These options are illustrated in Figure 6-6 and Figure 6-7. For input clock frequencies between 12 and 20 MHz, a crystal with 80 ohm max ESR is recommended. For input clock frequencies between 20 and 30 MHz, a crystal with 60 ohm max ESR is recommended. Typical load capacitance values are 10-20 pF, where the load capacitance is the series combination of C1 and C2.

The CLKMODE bit in the PLLCTL register must be 0 to use the on-chip oscillator. If CLKMODE is set to 1, the internal oscillator is disabled.

Figure 6-6 illustrates the option that uses on-chip 1.2V oscillator with external crystal circuit. Figure 6-7 illustrates the option that uses an external 1.2V clock input.

Figure 6-6 On-Chip Oscillator

Table 6-2 Oscillator Timing Requirements

PARAMETER		MIN	MAX	UNIT
f_osc	Oscillator frequency range (OSCIN/OSCOUT)	12	30	MHz

TMS320C6746 extended_1-2v_clock_prs483.gif

Figure 6-7 External 1.2V Clock Source

Table 6-3 OSCIN Timing Requirements for an Externally Driven Clock

PARAMETER		MIN	MAX	UNIT
f_OSCIN	OSCIN frequency range	12	50	MHz
t_c(OSCIN)	Cycle time, external clock driven on OSCIN	20		ns
t_w(OSCINH)	Pulse width high, external clock on OSCIN	0.4 t_c(OSCIN)		ns
t_w(OSCINL)	Pulse width low, external clock on OSCIN	0.4 t_c(OSCIN)		ns
t_t(OSCIN)	Transition time, OSCIN		0.25P or 10 ⁽¹⁾	ns
t_j(OSCIN)	Period jitter, OSCIN		0.02P	ns

(1) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input signals.

6.6 Clock PLLs

The device has two PLL controllers that provide clocks to different parts of the system. PLL0 provides clocks (though various dividers) to most of the components of the device. PLL1 provides clocks to the DDR2/mDDR Controller and provides an alternate clock source for the ASYNC3 clock domain. This allows the peripherals on the ASYNC3 clock domain to be immune to frequency scaling operation on PLL0.

The PLL controller provides the following:

Glitch-Free Transitions (on changing clock settings)
Domain Clocks Alignment
Clock Gating
PLL power down

The various clock outputs given by the controller are as follows:

Domain Clocks: SYSCLK [1:n]
Auxiliary Clock from reference clock source: AUXCLK

Various dividers that can be used are as follows:

Post-PLL Divider: POSTDIV
SYSCLK Divider: D1, ¼, Dn

Various other controls supported are as follows:

PLL Multiplier Control: PLLM
Software programmable PLL Bypass: PLLEN

6.6.1 PLL Device-Specific Information

The device DSP generates the high-frequency internal clocks it requires through an on-chip PLL.

The PLL requires some external filtering components to reduce power supply noise as shown in Figure 6-8.

Figure 6-8 PLL External Filtering Components

The external filtering components shown above provide noise immunity for the PLLs. PLL0_VDDA and PLL1_VDDA should not be connected together to provide noise immunity between the two PLLs. Likewise, PLL0_VSSA and PLL1_VSSA should not be connected together.

The input to the PLL is either from the on-chip oscillator or from an external clock on the OSCIN pin. PLL0 outputs seven clocks that have programmable divider options. PLL1 outputs three clocks that have programmable divider options. Figure 6-9 illustrates the high-level view of the PLL Topology.

The PLLs are disabled by default after a device reset. They must be configured by software according to the allowable operating conditions listed in Table 6-4 before enabling the device to run from the PLL by setting PLLEN = 1.

Figure 6-9 PLL Topology

Table 6-4 Allowed PLL Operating Conditions (PLL0 and PLL1)

NO.	PARAMETER	Default Value	MIN	MAX	UNIT
1	PLLRST: Assertion time during initialization	N/A	1000	N/A	ns
2	Lock time: The time that the application has to wait for the PLL to acquire lock before setting PLLEN, after changing PREDIV, PLLM, or OSCIN	N/A	N/A	⁽¹⁾	OSCIN cycles
3	PREDIV: Pre-divider value	/1	/1	/32	-
4	PLLREF: PLL input frequency		12	30 (if internal oscillator is used) 50 (if external clock is used)	MHz
5	PLLM: PLL multiplier values	x20	x4	x32
6	PLLOUT: PLL output frequency	N/A	300	600	MHz
7	POSTDIV: Post-divider value	/1	/1	/32	-

(1) The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 300 and 600 MHz, but the frequency going into the SYSCLK dividers (after the post divider) cannot exceed the maximum clock frequency defined for the device at a given voltage operating point.

6.6.2 Device Clock Generation

PLL0 is controlled by PLL Controller 0 and PLL1 is controlled by PLL Controller 1. PLLC0 and PLLC1 manage the clock ratios, alignment, and gating for the system clocks to the chip. The PLLCs are responsible for controlling all modes of the PLL through software, in terms of pre-division of the clock inputs (PLLC0 only), multiply factors within the PLLs, and post-division for each of the chip-level clocks from the PLLs outputs. PLLC0 also controls reset propagation through the chip, clock alignment, and test points.

PLLC0 provides clocks for the majority of the system but PLLC1 provides clocks to the DDR2/mDDR Controller and the ASYNC3 clock domain to provide frequency scaling immunity to a defined set or peripherals. The ASYNC3 clock domain can either derive its clock from PLL1_SYSCLK2 (for frequency scaling immunity from PLL0) or from PLL0_SYSCLK2 (for synchronous timing with PLL0) depending on the application requirements. In addition, some peripherals have specific clock options independent of the ASYNC clock domain.

6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)

The processor supports multiple operating points by scaling voltage and frequency to minimize power consumption for a given level of processor performance.

Frequency scaling is achieved by modifying the setting of the PLL controllers’ multipliers, post-dividers (POSTDIV), and system clock dividers (SYSCLKn). Modification of the POSTDIV and SYSCLK values does not require relocking the PLL and provides lower latency to switch between operating points, but at the expense of the frequencies being limited by the integer divide values (only the divide values are altered the PLL multiplier is left unmodified). Non integer divide frequency values can be achieved by changing both the multiplier and the divide values, but when the PLL multiplier is changed the PLL must relock, incurring additional latency to change between operating points. Detailed information on modifying the PLL Controller settings can be found in the TMS320C6746 DSP System Reference Guide (SPRUGM6).

Voltage scaling is enabled from outside the device by controlling an external voltage regulator. The processor may communicate with the regulator using GPIOs, I2C or some other interface. When switching between voltage-frequency operating points, the voltage must always support the desired frequency. When moving from a high-performance operating point to a lower performance operating point, the frequency should be lowered first followed by the voltage. When moving from a low-performance operating point to a higher performance operating point, the voltage should be raised first followed by the frequency. Voltage operating points refer to the CVdd voltage at that point. Other static supplies must be maintained at their nominal voltages at all operating points.

The maximum voltage slew rate for CVdd supply changes is 1 mV/us.

For additional information on power management solutions from TI for this processor, follow the Power Management link in the Product Folder on www.ti.com for this processor.

The processor supports multiple clock domains some of which have clock ratio requirements to each other. SYSCLK1:SYSCLK2:SYSCLK4:SYSCLK6 are synchronous to each other and the SYSCLKn dividers must always be configured such that the ratio between these domains is 1:2:4:1. The ASYNC and ASYNC3 clock domains are asynchronous to the other clock domains and have no specific ratio requirement.

Table 6-5 summarizes the maximum internal clock frequencies at each of the voltage operating points.

Table 6-5 Maximum Internal Clock Frequencies at Each Voltage Operating Point

CLOCK SOURCE	CLOCK DOMAIN		1.3V NOM	1.2V NOM	1.1V NOM	1.0V NOM
PLL0_SYSCLK1	DSP subsystem		456 MHz	375 MHz	200 MHz	100 MHz
PLL0_SYSCLK2	SYSCLK2 clock domain peripherals and optional clock source for ASYNC3 clock domain peripherals		228 MHz	187.5 MHz	100 MHz	50 MHz
PLL0_SYSCLK3	Optional clock for ASYNC1 clock domain (See ASYNC1 row)
PLL0_SYSCLK4	SYSCLK4 domain peripherals		114 MHz	93.75 MHz	50 MHz	25 MHz
PLL0_SYSCLK5	Not used on this processor		-	-	-	-
PLL0_SYSCLK6	Not used on this processor		-	-	-	-
PLL0_SYSCLK7	Optional 50 MHz clock source for EMAC RMII interface		50 MHz	50 MHz	-	-
PLL1_SYSCLK1	DDR2/mDDR Interface clock source (memory interface clock is one-half of the value shown)		312 MHz	312 MHz	300 MHz	266 MHz
PLL1_SYSCLK2	Optional clock source for ASYNC3 clock domain peripherals		152 MHz	150 MHz	100 MHz	75 MHz
PLL1_SYSCLK3	Alternate clock source input to PLL Controller 0		75 MHz	75 MHz	75 MHz	75 MHz
McASP AUXCLK	Bypass clock source for the McASP		50 MHz	50 MHz	50 MHz	50 MHz
PLL0_AUXCLK	Bypass clock source for the USB0		48 MHz	48 MHz	48 MHz	48 MHz
ASYNC1	ASYNC Clock Domain (EMIFA)	Async Mode	148 MHz	148 MHz	75 MHz	50 MHz
ASYNC1	ASYNC Clock Domain (EMIFA)	SDRAM Mode	100 MHz	100 MHz	66.6 MHz	50 MHz
ASYNC2	ASYNC2 Clock Domain (multiple peripherals)		50 MHz	50 MHz	50 MHz	50 MHz

Some interfaces have specific limitations on supported modes/speeds at each operating point. See the corresponding peripheral sections of this document for more information.

TI provides software components (called the Power Manager) to perform DVFS and abstract the task from the user. The Power Manager controls changing operating points (both frequency and voltage) and handles the related tasks involved such as informing/controlling peripherals to provide graceful transitions between operating points. The Power Manager is bundled as a component of DSP/BIOS.

6.7 Interrupts

The device has a large number of interrupts to service the needs of its many peripherals and subsystems.

6.7.1 DSP Interrupts

The C674x DSP interrupt controller combines device events into 12 prioritized interrupts. The source for each of the 12 CPU interrupts is user programmable and is listed in Table 6-6. Also, the interrupt controller controls the generation of the CPU exceptions, NMI, and emulation interrupts. Table 6-7 summarizes the C674x interrupt controller registers and memory locations.

Refer to the C674x DSP MegaModule Reference Guide (SPRUFK5) and the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8) for details of the C674x interrupts.

Table 6-6 C6746 DSP Interrupts

EVT#	Interrupt Name	Source
0	EVT0	C674x Int Ctl 0
1	EVT1	C674x Int Ctl 1
2	EVT2	C674x Int Ctl 2
3	EVT3	C674x Int Ctl 3
4	T64P0_TINT12	Timer64P0 - TINT12
5	SYSCFG_CHIPINT2	SYSCFG CHIPSIG Register
6	PRU_EVTOUT0	PRUSS Interrupt
7	EHRPWM0	HiResTimer/PWM0 Interrupt
8	EDMA3_0_CC0_INT1	EDMA3_0 Channel Controller 0 Shadow Region 1 Transfer Completion Interrupt
9	EMU_DTDMA	C674x-ECM
10	EHRPWM0TZ	HiResTimer/PWM0 Trip Zone Interrupt
11	EMU_RTDXRX	C674x-RTDX
12	EMU_RTDXTX	C674x-RTDX
13	IDMAINT0	C674x-EMC
14	IDMAINT1	C674x-EMC
15	MMCSD0_INT0	MMCSD0 MMC/SD Interrupt
16	MMCSD0_INT1	MMCSD0 SDIO Interrupt
17	PRU_EVTOUT1	PRUSS Interrupt
18	EHRPWM1	HiResTimer/PWM1 Interrupt
19	USB0_INT	USB0 Interrupt
20-21	-	Reserved
22	PRU_EVTOUT2	PRUSS Interrupt
23	EHRPWM1TZ	HiResTimer/PWM1 Trip Zone Interrupt
24	-	Reserved
25	T64P2_TINTALL	Timer64P2 Combined TINT12 and TINT 34 Interrupt
26	EMAC_C0RXTHRESH	EMAC - Core 0 Receive Threshold Interrupt
27	EMAC_C0RX	EMAC - Core 0 Receive Interrupt
28	EMAC_C0TX	EMAC - Core 0 Transmit Interrupt
29	EMAC_C0MISC	EMAC - Core 0 Miscellaneous Interrupt
30	EMAC_C1RXTHRESH	EMAC - Core 1 Receive Threshold Interrupt
31	EMAC_C1RX	EMAC - Core 1 Receive Interrupt
32	EMAC_C1TX	EMAC - Core 1 Transmit Interrupt
33	EMAC_C1MISC	EMAC - Core 1 Miscellaneous Interrupt
34	UHPI_DSPINT	UHPI DSP Interrupt
35	PRU_EVTOUT3	PRUSS Interrupt
36	IIC0_INT	I2C0
37	SP0_INT	SPI0
38	UART0_INT	UART0
39	PRU_EVTOUT5	PRUSS Interrupt
40	T64P1_TINT12	Timer64P1 Interrupt 12
41	GPIO_B1INT	GPIO Bank 1 Interrupt
42	IIC1_INT	I2C1
43	SPI1_INT	SPI1
44	PRU_EVTOUT6	PRUSS Interrupt
45	ECAP0	ECAP0
46	UART_INT1	UART1
47	ECAP1	ECAP1
48	T64P1_TINT34	Timer64P1 Interrupt 34
49	GPIO_B2INT	GPIO Bank 2 Interrupt
50	PRU_EVTOUT7	PRUSS Interrupt
51	ECAP2	ECAP2
52	GPIO_B3INT	GPIO Bank 3 Interrupt
53	MMCSD1_INT1	MMCSD1 SDIO Interrupt
54	GPIO_B4INT	GPIO Bank 4 Interrupt
55	EMIFA_INT	EMIFA
56	EDMA3_0_CC0_ERRINT	EDMA3_0 Channel Controller 0 Error Interrupt
57	EDMA3_0_TC0_ERRINT	EDMA3_0 Transfer Controller 0 Error Interrupt
58	EDMA3_0_TC1_ERRINT	EDMA3_0 Transfer Controller 1 Error Interrupt
59	GPIO_B5INT	GPIO Bank 5 Interrupt
60	DDR2_MEMERR	DDR2 Memory Error Interrupt
61	MCASP0_INT	McASP0 Combined RX/TX Interrupts
62	GPIO_B6INT	GPIO Bank 6 Interrupt
63	RTC_IRQS	RTC Combined
64	T64P0_TINT34	Timer64P0 Interrupt 34
65	GPIO_B0INT	GPIO Bank 0 Interrupt
66	PRU_EVTOUT4	PRUSS Interrupt
67	SYSCFG_CHIPINT3	SYSCFG_CHIPSIG Register
68	MMCSD1_INT0	MMCSD1 MMC/SD Interrupt
69	UART2_INT	UART2
70	PSC0_ALLINT	PSC0
71	PSC1_ALLINT	PSC1
72	GPIO_B7INT	GPIO Bank 7 Interrupt
73	-	Reserved
74	PROTERR	SYSCFG Protection Shared Interrupt
75	GPIO_B8INT	GPIO Bank 8 Interrupt
76 - 77	-	Reserved
78	T64P2_CMPINT0	Timer64P2 - Compare Interrupt 0
79	T64P2_CMPINT1	Timer64P2 - Compare Interrupt 1
80	T64P2_CMPINT2	Timer64P2 - Compare Interrupt 2
81	T64P2_CMPINT3	Timer64P2 - Compare Interrupt 3
82	T64P2_CMPINT4	Timer64P2 - Compare Interrupt 4
83	T64P2_CMPINT5	Timer64P2 - Compare Interrupt 5
84	T64P2_CMPINT6	Timer64P2 - Compare Interrupt 6
85	T64P2_CMPINT7	Timer64P2 - Compare Interrupt 7
86	T64P3_TINTALL	Timer64P3 Combined TINT12 and TINT 34 Interrupt
87	MCBSP0_RINT	McBSP0 Receive Interrupt
88	MCBSP0_XINT	McBSP0 Transmit Interrupt
89	MCBSP1_RINT	McBSP1 Receive Interrupt
90	MCBSP1_XINT	McBSP1 Transmit Interrupt
91	EDMA3_1_CC0_INT1	EDMA3_1 Channel Controller 0 Shadow Region 1 Transfer Completion Interrupt
92	EDMA3_1_CC0_ERRINT	EDMA3_1 Channel Controller 0 Error Interrupt
93	EDMA3_1_TC0_ERRINT	EDMA3_1 Transfer Controller 0 Error Interrupt
94	UPP_INT	uPP Combined Interrupt
95	VPIF_INT	VPIF Combined Interrupt
96	INTERR	C674x-Int Ctl
97	EMC_IDMAERR	C674x-EMC
98 - 112	-	Reserved
113	PMC_ED	C674x-PMC
114 - 115	-	Reserved
116	UMC_ED1	C674x-UMC
117	UMC_ED2	C674x-UMC
118	PDC_INT	C674x-PDC
119	SYS_CMPA	C674x-SYS
120	PMC_CMPA	C674x-PMC
121	PMC_CMPA	C674x-PMC
122	DMC_CMPA	C674x-DMC
123	DMC_CMPA	C674x-DMC
124	UMC_CMPA	C674x-UMC
125	UMC_CMPA	C674x-UMC
126	EMC_CMPA	C674x-EMC
127	EMC_BUSERR	C674x-EMC

Table 6-7 C674x DSP Interrupt Controller Registers

BYTE ADDRESS	ACRONYM	DESCRIPTION
0x0180 0000	EVTFLAG0	Event flag register 0
0x0180 0004	EVTFLAG1	Event flag register 1
0x0180 0008	EVTFLAG2	Event flag register 2
0x0180 000C	EVTFLAG3	Event flag register 3
0x0180 0020	EVTSET0	Event set register 0
0x0180 0024	EVTSET1	Event set register 1
0x0180 0028	EVTSET2	Event set register 2
0x0180 002C	EVTSET3	Event set register 3
0x0180 0040	EVTCLR0	Event clear register 0
0x0180 0044	EVTCLR1	Event clear register 1
0x0180 0048	EVTCLR2	Event clear register 2
0x0180 004C	EVTCLR3	Event clear register 3
0x0180 0080	EVTMASK0	Event mask register 0
0x0180 0084	EVTMASK1	Event mask register 1
0x0180 0088	EVTMASK2	Event mask register 2
0x0180 008C	EVTMASK3	Event mask register 3
0x0180 00A0	MEVTFLAG0	Masked event flag register 0
0x0180 00A4	MEVTFLAG1	Masked event flag register 1
0x0180 00A8	MEVTFLAG2	Masked event flag register 2
0x0180 00AC	MEVTFLAG3	Masked event flag register 3
0x0180 00C0	EXPMASK0	Exception mask register 0
0x0180 00C4	EXPMASK1	Exception mask register 1
0x0180 00C8	EXPMASK2	Exception mask register 2
0x0180 00CC	EXPMASK3	Exception mask register 3
0x0180 00E0	MEXPFLAG0	Masked exception flag register 0
0x0180 00E4	MEXPFLAG1	Masked exception flag register 1
0x0180 00E8	MEXPFLAG2	Masked exception flag register 2
0x0180 00EC	MEXPFLAG3	Masked exception flag register 3
0x0180 0104	INTMUX1	Interrupt mux register 1
0x0180 0108	INTMUX2	Interrupt mux register 2
0x0180 010C	INTMUX3	Interrupt mux register 3
0x0180 0140 - 0x0180 0144	-	Reserved
0x0180 0180	INTXSTAT	Interrupt exception status
0x0180 0184	INTXCLR	Interrupt exception clear
0x0180 0188	INTDMASK	Dropped interrupt mask register
0x0180 01C0	EVTASRT	Event assert register

6.8 Power and Sleep Controller (PSC)

The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off, clock on/off, resets (device level and module level). It is used primarily to provide granular power control for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC and provides clock and reset control.

The PSC includes the following features:

Provides a software interface to:
- Control module clock enable/disable
- Control module reset
- Control CPU local reset
Supports IcePick emulation features: power, clock and reset

PSC0 controls 16 local PSCs.

PSC1 controls 32 local PSCs.

Table 6-8 Power and Sleep Controller (PSC) Registers

PSC0 BYTE ADDRESS	PSC1 BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01C1 0000	0x01E2 7000	REVID	Peripheral Revision and Class Information Register
0x01C1 0018	0x01E2 7018	INTEVAL	Interrupt Evaluation Register
0x01C1 0040	0x01E2 7040	MERRPR0	Module Error Pending Register 0 (module 0-15) (PSC0)
0x01C1 0040	0x01E2 7040	MERRPR0	Module Error Pending Register 0 (module 0-31) (PSC1)
0x01C1 0050	0x01E2 7050	MERRCR0	Module Error Clear Register 0 (module 0-15) (PSC0)
0x01C1 0050	0x01E2 7050	MERRCR0	Module Error Clear Register 0 (module 0-31) (PSC1)
0x01C1 0060	0x01E2 7060	PERRPR	Power Error Pending Register
0x01C1 0068	0x01E2 7068	PERRCR	Power Error Clear Register
0x01C1 0120	0x01E2 7120	PTCMD	Power Domain Transition Command Register
0x01C1 0128	0x01E2 7128	PTSTAT	Power Domain Transition Status Register
0x01C1 0200	0x01E2 7200	PDSTAT0	Power Domain 0 Status Register
0x01C1 0204	0x01E2 7204	PDSTAT1	Power Domain 1 Status Register
0x01C1 0300	0x01E2 7300	PDCTL0	Power Domain 0 Control Register
0x01C1 0304	0x01E2 7304	PDCTL1	Power Domain 1 Control Register
0x01C1 0400	0x01E2 7400	PDCFG0	Power Domain 0 Configuration Register
0x01C1 0404	0x01E2 7404	PDCFG1	Power Domain 1 Configuration Register
0x01C1 0800	0x01E2 7800	MDSTAT0	Module 0 Status Register
0x01C1 0804	0x01E2 7804	MDSTAT1	Module 1 Status Register
0x01C1 0808	0x01E2 7808	MDSTAT2	Module 2 Status Register
0x01C1 080C	0x01E2 780C	MDSTAT3	Module 3 Status Register
0x01C1 0810	0x01E2 7810	MDSTAT4	Module 4 Status Register
0x01C1 0814	0x01E2 7814	MDSTAT5	Module 5 Status Register
0x01C1 0818	0x01E2 7818	MDSTAT6	Module 6 Status Register
0x01C1 081C	0x01E2 781C	MDSTAT7	Module 7 Status Register
0x01C1 0820	0x01E2 7820	MDSTAT8	Module 8 Status Register
0x01C1 0824	0x01E2 7824	MDSTAT9	Module 9 Status Register
0x01C1 0828	0x01E2 7828	MDSTAT10	Module 10 Status Register
0x01C1 082C	0x01E2 782C	MDSTAT11	Module 11 Status Register
0x01C1 0830	0x01E2 7830	MDSTAT12	Module 12 Status Register
0x01C1 0834	0x01E2 7834	MDSTAT13	Module 13 Status Register
0x01C1 0838	0x01E2 7838	MDSTAT14	Module 14 Status Register
0x01C1 083C	0x01E2 783C	MDSTAT15	Module 15 Status Register
-	0x01E2 7840	MDSTAT16	Module 16 Status Register
-	0x01E2 7844	MDSTAT17	Module 17 Status Register
-	0x01E2 7848	MDSTAT18	Module 18 Status Register
-	0x01E2 784C	MDSTAT19	Module 19 Status Register
-	0x01E2 7850	MDSTAT20	Module 20 Status Register
-	0x01E2 7854	MDSTAT21	Module 21 Status Register
-	0x01E2 7858	MDSTAT22	Module 22 Status Register
-	0x01E2 785C	MDSTAT23	Module 23 Status Register
-	0x01E2 7860	MDSTAT24	Module 24 Status Register
-	0x01E2 7864	MDSTAT25	Module 25 Status Register
-	0x01E2 7868	MDSTAT26	Module 26 Status Register
-	0x01E2 786C	MDSTAT27	Module 27 Status Register
-	0x01E2 7870	MDSTAT28	Module 28 Status Register
-	0x01E2 7874	MDSTAT29	Module 29 Status Register
-	0x01E2 7878	MDSTAT30	Module 30 Status Register
-	0x01E2 787C	MDSTAT31	Module 31 Status Register
0x01C1 0A00	0x01E2 7A00	MDCTL0	Module 0 Control Register
0x01C1 0A04	0x01E2 7A04	MDCTL1	Module 1 Control Register
0x01C1 0A08	0x01E2 7A08	MDCTL2	Module 2 Control Register
0x01C1 0A0C	0x01E2 7A0C	MDCTL3	Module 3 Control Register
0x01C1 0A10	0x01E2 7A10	MDCTL4	Module 4 Control Register
0x01C1 0A14	0x01E2 7A14	MDCTL5	Module 5 Control Register
0x01C1 0A18	0x01E2 7A18	MDCTL6	Module 6 Control Register
0x01C1 0A1C	0x01E2 7A1C	MDCTL7	Module 7 Control Register
0x01C1 0A20	0x01E2 7A20	MDCTL8	Module 8 Control Register
0x01C1 0A24	0x01E2 7A24	MDCTL9	Module 9 Control Register
0x01C1 0A28	0x01E2 7A28	MDCTL10	Module 10 Control Register
0x01C1 0A2C	0x01E2 7A2C	MDCTL11	Module 11 Control Register
0x01C1 0A30	0x01E2 7A30	MDCTL12	Module 12 Control Register
0x01C1 0A34	0x01E2 7A34	MDCTL13	Module 13 Control Register
0x01C1 0A38	0x01E2 7A38	MDCTL14	Module 14 Control Register
0x01C1 0A3C	0x01E2 7A3C	MDCTL15	Module 15 Control Register
-	0x01E2 7A40	MDCTL16	Module 16 Control Register
-	0x01E2 7A44	MDCTL17	Module 17 Control Register
-	0x01E2 7A48	MDCTL18	Module 18 Control Register
-	0x01E2 7A4C	MDCTL19	Module 19 Control Register
-	0x01E2 7A50	MDCTL20	Module 20 Control Register
-	0x01E2 7A54	MDCTL21	Module 21 Control Register
-	0x01E2 7A58	MDCTL22	Module 22 Control Register
-	0x01E2 7A5C	MDCTL23	Module 23 Control Register
-	0x01E2 7A60	MDCTL24	Module 24 Control Register
-	0x01E2 7A64	MDCTL25	Module 25 Control Register
-	0x01E2 7A68	MDCTL26	Module 26 Control Register
-	0x01E2 7A6C	MDCTL27	Module 27 Control Register
-	0x01E2 7A70	MDCTL28	Module 28 Control Register
-	0x01E2 7A74	MDCTL29	Module 29 Control Register
-	0x01E2 7A78	MDCTL30	Module 30 Control Register
-	0x01E2 7A7C	MDCTL31	Module 31 Control Register

6.8.1 Power Domain and Module Topology

The device includes two PSC modules.

Each PSC module controls clock states for several of the on chip modules, controllers and interconnect components. Table 6-9 and Table 6-10 lists the set of peripherals/modules that are controlled by the PSC, the power domain they are associated with, the LPSC assignment and the default (power-on reset) module states. The module states and terminology are defined in Section 6.8.1.2.

Table 6-9 PSC0 Default Module Configuration

LPSC Number	Module Name	Power Domain	Default Module State	Auto Sleep/Wake Only
0	EDMA3 Channel Controller 0	AlwaysON (PD0)	SwRstDisable	—
1	EDMA3 Transfer Controller 0	AlwaysON (PD0)	SwRstDisable	—
2	EDMA3 Transfer Controller 1	AlwaysON (PD0)	SwRstDisable	—
3	EMIFA (Br7)	AlwaysON (PD0)	SwRstDisable	—
4	SPI 0	AlwaysON (PD0)	SwRstDisable	—
5	MMC/SD 0	AlwaysON (PD0)	SwRstDisable	—
6	—	—	—	—
7	—	—	—	—
8	—	—	—	—
9	UART 0	AlwaysON (PD0)	SwRstDisable	—
10	SCR0 (Br 0, Br 1, Br 2, Br 8)	AlwaysON (PD0)	Enable	Yes
11	SCR1 (Br 4)	AlwaysON (PD0)	Enable	Yes
12	SCR2 (Br 3, Br 5, Br 6)	AlwaysON (PD0)	Enable	Yes
13	PRUSS	AlwaysON (PD0)	SwRstDisable	—
14	—	—	—	—
15	DSP	PD_DSP (PD1)	Enable	—

Table 6-10 PSC1 Default Module Configuration

LPSC Number	Module Name	Power Domain	Default Module State	Auto Sleep/Wake Only
0	EDMA3 Channel Controller 1	AlwaysON (PD0)	SwRstDisable	—
1	USB0 (USB2.0)	AlwaysON (PD0)	SwRstDisable	—
2	—	—	—	—
3	GPIO	AlwaysON (PD0)	SwRstDisable	—
4	UHPI	AlwaysON (PD0)	SwRstDisable	—
5	EMAC	AlwaysON (PD0)	SwRstDisable	—
6	DDR2 (and SCR_F3)	AlwaysON (PD0)	SwRstDisable	—
7	McASP0 ( + McASP0 FIFO)	AlwaysON (PD0)	SwRstDisable	—
8	—	—	—	—
9	VPIF	AlwaysON (PD0)	SwRstDisable	—
10	SPI 1	AlwaysON (PD0)	SwRstDisable	—
11	I2C 1	AlwaysON (PD0)	SwRstDisable	—
12	UART 1	AlwaysON (PD0)	SwRstDisable	—
13	UART 2	AlwaysON (PD0)	SwRstDisable	—
14	McBSP0 ( + McBSP0 FIFO)	AlwaysON (PD0)	SwRstDisable	—
15	McBSP1 ( + McBSP1 FIFO)	AlwaysON (PD0)	SwRstDisable	—
16	—	—	—	—
17	eHRPWM0/1	AlwaysON (PD0)	SwRstDisable	—
18	MMCSD1	AlwaysON (PD0)	SwRstDisable	—
19	uPP	AlwaysON (PD0)	SwRstDisable	—
20	ECAP0/1/2	AlwaysON (PD0)	SwRstDisable	—
21	EDMA3 Transfer Controller 2	AlwaysON (PD0)	SwRstDisable	—
22	—	—	—	—
23	—	—	—	—
24	SCR_F0 (and bridge F0)	AlwaysON (PD0)	Enable	Yes
25	SCR_F1 (and bridge F1)	AlwaysON (PD0)	Enable	Yes
26	SCR_F2 (and bridge F2)	AlwaysON (PD0)	Enable	Yes
27	SCR_F6 (and bridge F3)	AlwaysON (PD0)	Enable	Yes
28	SCR_F7 (and bridge F4)	AlwaysON (PD0)	Enable	Yes
29	SCR_F8 (and bridge F5)	AlwaysON (PD0)	Enable	Yes
30	Bridge F7 (DDR Controller path)	AlwaysON (PD0)	Enable	Yes
31	—	—	—	—

6.8.1.1 Power Domain States

A power domain can only be in one of the two states: ON or OFF, defined as follows:

ON: power to the domain is on
OFF: power to the domain is off

For both PSC0 and PSC1, the Always ON domain, or PD0 power domain, is always in the ON state when the chip is powered-on. This domain is not programmable to OFF state.

On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories

6.8.1.2 Module States

The PSC defines several possible states for a module. This states are essentially a combination of the module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are defined in Table 6-11.

Table 6-11 Module States

Module State	Module Reset	Module Clock	Module State Definition
Enable	De-asserted	On	A module in the enable state has its module reset de-asserted and it has its clock on. This is the normal operational state for a given module
Disable	De-asserted	Off	A module in the disabled state has its module reset de-asserted and it has its module clock off. This state is typically used for disabling a module clock to save power. The device is designed in full static CMOS, so when you stop a module clock, it retains the module’s state. When the clock is restarted, the module resumes operating from the stopping point.
SyncReset	Asserted	On	A module state in the SyncReset state has its module reset asserted and it has its clock on. Generally, software is not expected to initiate this state
SwRstDisable	Asserted	Off	A module in the SwResetDisable state has its module reset asserted and it has its clock disabled. After initial power-on, several modules come up in the SwRstDisable state. Generally, software is not expected to initiate this state
Auto Sleep	De-asserted	Off	A module in the Auto Sleep state also has its module reset de-asserted and its module clock disabled, similar to the Disable state. However this is a special state, once a module is configured in this state by software, it can “automatically” transition to “Enable” state whenever there is an internal read/write request made to it, and after servicing the request it will “automatically” transition into the sleep state (with module reset re de-asserted and module clock disabled), without any software intervention. The transition from sleep to enabled and back to sleep state has some cycle latency associated with it. It is not envisioned to use this mode when peripherals are fully operational and moving data.
Auto Wake	De-asserted	Off	A module in the Auto Wake state also has its module reset de-asserted and its module clock disabled, similar to the Disable state. However this is a special state, once a module is configured in this state by software, it will “automatically” transition to “Enable” state whenever there is an internal read/write request made to it, and will remain in the “Enabled” state from then on (with module reset re de-asserted and module clock on), without any software intervention. The transition from sleep to enabled state has some cycle latency associated with it. It is not envisioned to use this mode when peripherals are fully operational and moving data.

6.9 Enhanced Direct Memory Access Controller (EDMA3)

The EDMA3 controller handles all data transfers between memories and the device slave peripherals on the device. These data transfers include cache servicing, non-cacheable memory accesses, user-programmed data transfers, and host accesses.

6.9.1 EDMA3 Channel Synchronization Events

Each EDMA3 channel controller supports up to 32 channels which service peripherals and memory. Table 6-12 lists the source of the EDMA3 synchronization events associated with each of the programmable EDMA channels.

Table 6-12 EDMA Synchronization Events

EDMA3 Channel Controller 0
Event	Event Name / Source	Event	Event Name / Source
0	McASP0 Receive	16	MMCSD0 Receive
1	McASP0 Transmit	17	MMCSD0 Transmit
2	McBSP0 Receive	18	SPI1 Receive
3	McBSP0 Transmit	19	SPI1 Transmit
4	McBSP1 Receive	20	PRU_EVTOUT6
5	McBSP1 Transmit	21	PRU_EVTOUT7
6	GPIO Bank 0 Interrupt	22	GPIO Bank 2 Interrupt
7	GPIO Bank 1 Interrupt	23	GPIO Bank 3 Interrupt
8	UART0 Receive	24	I2C0 Receive
9	UART0 Transmit	25	I2C0 Transmit
10	Timer64P0 Event Out 12	26	I2C1 Receive
11	Timer64P0 Event Out 34	27	I2C1 Transmit
12	UART1 Receive	28	GPIO Bank 4 Interrupt
13	UART1 Transmit	29	GPIO Bank 5 Interrupt
14	SPI0 Receive	30	UART2 Receive
15	SPI0 Transmit	31	UART2 Transmit
EDMA3 Channel Controller 1
Event	Event Name / Source	Event	Event Name / Source
0	Timer64P2 Compare Event 0	16	GPIO Bank 6 Interrupt
1	Timer64P2 Compare Event 1	17	GPIO Bank 7 Interrupt
2	Timer64P2 Compare Event 2	18	GPIO Bank 8 Interrupt
3	Timer64P2 Compare Event 3	19	Reserved
4	Timer64P2 Compare Event 4	20	Reserved
5	Timer64P2 Compare Event 5	21	Reserved
6	Timer64P2 Compare Event 6	22	Reserved
7	Timer64P2 Compare Event 7	23	Reserved
8	Timer64P3 Compare Event 0	24	Timer64P2 Event Out 12
9	Timer64P3 Compare Event 1	25	Timer64P2 Event Out 34
10	Timer64P3 Compare Event 2	26	Timer64P3 Event Out 12
11	Timer64P3 Compare Event 3	27	Timer64P3 Event Out 34
12	Timer64P3 Compare Event 4	28	MMCSD1 Receive
13	Timer64P3 Compare Event 5	29	MMCSD1 Transmit
14	Timer64P3 Compare Event 6	30	Reserved
15	Timer64P3 Compare Event 7	31	Reserved

6.9.2 EDMA3 Peripheral Register Descriptions

Table 6-13 is the list of EDMA3 Channel Controller Registers and Table 6-14 is the list of EDMA3 Transfer Controller registers.

Table 6-13 EDMA3 Channel Controller (EDMA3CC) Registers

EDMA3_0 Channel Controller 0 BYTE ADDRESS	EDMA3_1 Channel Controller 0 BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01C0 0000	0x01E3 0000	PID	Peripheral Identification Register
0x01C0 0004	0x01E3 0004	CCCFG	EDMA3CC Configuration Register
Global Registers
0x01C0 0200	0x01E3 0200	QCHMAP0	QDMA Channel 0 Mapping Register
0x01C0 0204	0x01E3 0204	QCHMAP1	QDMA Channel 1 Mapping Register
0x01C0 0208	0x01E3 0208	QCHMAP2	QDMA Channel 2 Mapping Register
0x01C0 020C	0x01E3 020C	QCHMAP3	QDMA Channel 3 Mapping Register
0x01C0 0210	0x01E3 0210	QCHMAP4	QDMA Channel 4 Mapping Register
0x01C0 0214	0x01E3 0214	QCHMAP5	QDMA Channel 5 Mapping Register
0x01C0 0218	0x01E3 0218	QCHMAP6	QDMA Channel 6 Mapping Register
0x01C0 021C	0x01E3 021C	QCHMAP7	QDMA Channel 7 Mapping Register
0x01C0 0240	0x01E3 0240	DMAQNUM0	DMA Channel Queue Number Register 0
0x01C0 0244	0x01E3 0244	DMAQNUM1	DMA Channel Queue Number Register 1
0x01C0 0248	0x01E3 0248	DMAQNUM2	DMA Channel Queue Number Register 2
0x01C0 024C	0x01E3 024C	DMAQNUM3	DMA Channel Queue Number Register 3
0x01C0 0260	0x01E3 0260	QDMAQNUM	QDMA Channel Queue Number Register
0x01C0 0284	0x01E3 0284	QUEPRI	Queue Priority Register⁽¹⁾
0x01C0 0300	0x01E3 0300	EMR	Event Missed Register
0x01C0 0308	0x01E3 0308	EMCR	Event Missed Clear Register
0x01C0 0310	0x01E3 0310	QEMR	QDMA Event Missed Register
0x01C0 0314	0x01E3 0314	QEMCR	QDMA Event Missed Clear Register
0x01C0 0318	0x01E3 0318	CCERR	EDMA3CC Error Register
0x01C0 031C	0x01E3 031C	CCERRCLR	EDMA3CC Error Clear Register
0x01C0 0320	0x01E3 0320	EEVAL	Error Evaluate Register
0x01C0 0340	0x01E3 0340	DRAE0	DMA Region Access Enable Register for Region 0
0x01C0 0348	0x01E3 0348	DRAE1	DMA Region Access Enable Register for Region 1
0x01C0 0350	0x01E3 0350	DRAE2	DMA Region Access Enable Register for Region 2
0x01C0 0358	0x01E3 0358	DRAE3	DMA Region Access Enable Register for Region 3
0x01C0 0380	0x01E3 0380	QRAE0	QDMA Region Access Enable Register for Region 0
0x01C0 0384	0x01E3 0384	QRAE1	QDMA Region Access Enable Register for Region 1
0x01C0 0388	0x01E3 0388	QRAE2	QDMA Region Access Enable Register for Region 2
0x01C0 038C	0x01E3 038C	QRAE3	QDMA Region Access Enable Register for Region 3
0x01C0 0400 - 0x01C0 043C	0x01E3 0400 - 0x01E3 043C	Q0E0-Q0E15	Event Queue Entry Registers Q0E0-Q0E15
0x01C0 0440 - 0x01C0 047C	0x01E3 0440 - 0x01E3 047C	Q1E0-Q1E15	Event Queue Entry Registers Q1E0-Q1E15
0x01C0 0600	0x01E3 0600	QSTAT0	Queue 0 Status Register
0x01C0 0604	0x01E3 0604	QSTAT1	Queue 1 Status Register
0x01C0 0620	0x01E3 0620	QWMTHRA	Queue Watermark Threshold A Register
0x01C0 0640	0x01E3 0640	CCSTAT	EDMA3CC Status Register
Global Channel Registers
0x01C0 1000	0x01E3 1000	ER	Event Register
0x01C0 1008	0x01E3 1008	ECR	Event Clear Register
0x01C0 1010	0x01E3 1010	ESR	Event Set Register
0x01C0 1018	0x01E3 1018	CER	Chained Event Register
0x01C0 1020	0x01E3 1020	EER	Event Enable Register
0x01C0 1028	0x01E3 1028	EECR	Event Enable Clear Register
0x01C0 1030	0x01E3 1030	EESR	Event Enable Set Register
0x01C0 1038	0x01E3 1038	SER	Secondary Event Register
0x01C0 1040	0x01E3 1040	SECR	Secondary Event Clear Register
0x01C0 1050	0x01E3 1050	IER	Interrupt Enable Register
0x01C0 1058	0x01E3 1058	IECR	Interrupt Enable Clear Register
0x01C0 1060	0x01E3 1060	IESR	Interrupt Enable Set Register
0x01C0 1068	0x01E3 1068	IPR	Interrupt Pending Register
0x01C0 1070	0x01E3 1070	ICR	Interrupt Clear Register
0x01C0 1078	0x01E3 1078	IEVAL	Interrupt Evaluate Register
0x01C0 1080	0x01E3 1080	QER	QDMA Event Register
0x01C0 1084	0x01E3 1084	QEER	QDMA Event Enable Register
0x01C0 1088	0x01E3 1088	QEECR	QDMA Event Enable Clear Register
0x01C0 108C	0x01E3 108C	QEESR	QDMA Event Enable Set Register
0x01C0 1090	0x01E3 1090	QSER	QDMA Secondary Event Register
0x01C0 1094	0x01E3 1094	QSECR	QDMA Secondary Event Clear Register
Shadow Region 0 Channel Registers
0x01C0 2000	0x01E3 2000	ER	Event Register
0x01C0 2008	0x01E3 2008	ECR	Event Clear Register
0x01C0 2010	0x01E3 2010	ESR	Event Set Register
0x01C0 2018	0x01E3 2018	CER	Chained Event Register
0x01C0 2020	0x01E3 2020	EER	Event Enable Register
0x01C0 2028	0x01E3 2028	EECR	Event Enable Clear Register
0x01C0 2030	0x01E3 2030	EESR	Event Enable Set Register
0x01C0 2038	0x01E3 2038	SER	Secondary Event Register
0x01C0 2040	0x01E3 2040	SECR	Secondary Event Clear Register
0x01C0 2050	0x01E3 2050	IER	Interrupt Enable Register
0x01C0 2058	0x01E3 2058	IECR	Interrupt Enable Clear Register
0x01C0 2060	0x01E3 2060	IESR	Interrupt Enable Set Register
0x01C0 2068	0x01E3 2068	IPR	Interrupt Pending Register
0x01C0 2070	0x01E3 2070	ICR	Interrupt Clear Register
0x01C0 2078	0x01E3 2078	IEVAL	Interrupt Evaluate Register
0x01C0 2080	0x01E3 2080	QER	QDMA Event Register
0x01C0 2084	0x01E3 2084	QEER	QDMA Event Enable Register
0x01C0 2088	0x01E3 2088	QEECR	QDMA Event Enable Clear Register
0x01C0 208C	0x01E3 208C	QEESR	QDMA Event Enable Set Register
0x01C0 2090	0x01E3 2090	QSER	QDMA Secondary Event Register
0x01C0 2094	0x01E3 2094	QSECR	QDMA Secondary Event Clear Register
Shadow Region 1 Channel Registers
0x01C0 2200	0x01E3 2200	ER	Event Register
0x01C0 2208	0x01E3 2208	ECR	Event Clear Register
0x01C0 2210	0x01E3 2210	ESR	Event Set Register
0x01C0 2218	0x01E3 2218	CER	Chained Event Register
0x01C0 2220	0x01E3 2220	EER	Event Enable Register
0x01C0 2228	0x01E3 2228	EECR	Event Enable Clear Register
0x01C0 2230	0x01E3 2230	EESR	Event Enable Set Register
0x01C0 2238	0x01E3 2238	SER	Secondary Event Register
0x01C0 2240	0x01E3 2240	SECR	Secondary Event Clear Register
0x01C0 2250	0x01E3 2250	IER	Interrupt Enable Register
0x01C0 2258	0x01E3 2258	IECR	Interrupt Enable Clear Register
0x01C0 2260	0x01E3 2260	IESR	Interrupt Enable Set Register
0x01C0 2268	0x01E3 2268	IPR	Interrupt Pending Register
0x01C0 2270	0x01E3 2270	ICR	Interrupt Clear Register
0x01C0 2278	0x01E3 2278	IEVAL	Interrupt Evaluate Register
0x01C0 2280	0x01E3 2280	QER	QDMA Event Register
0x01C0 2284	0x01E3 2284	QEER	QDMA Event Enable Register
0x01C0 2288	0x01E3 2288	QEECR	QDMA Event Enable Clear Register
0x01C0 228C	0x01E3 228C	QEESR	QDMA Event Enable Set Register
0x01C0 2290	0x01E3 2290	QSER	QDMA Secondary Event Register
0x01C0 2294	0x01E3 2294	QSECR	QDMA Secondary Event Clear Register
0x01C0 4000 - 0x01C0 4FFF	0x01E3 4000 - 0x01E3 4FFF	—	Parameter RAM (PaRAM)

(1) On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC memory-map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.

Table 6-14 EDMA3 Transfer Controller (EDMA3TC) Registers

EDMA3_0 Transfer Controller 0 BYTE ADDRESS	EDMA3_0 Transfer Controller 1 BYTE ADDRESS	EDMA3_1 Transfer Controller 0 BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01C0 8000	0x01C0 8400	0x01E3 8000	PID	Peripheral Identification Register
0x01C0 8004	0x01C0 8404	0x01E3 8004	TCCFG	EDMA3TC Configuration Register
0x01C0 8100	0x01C0 8500	0x01E3 8100	TCSTAT	EDMA3TC Channel Status Register
0x01C0 8120	0x01C0 8520	0x01E3 8120	ERRSTAT	Error Status Register
0x01C0 8124	0x01C0 8524	0x01E3 8124	ERREN	Error Enable Register
0x01C0 8128	0x01C0 8528	0x01E3 8128	ERRCLR	Error Clear Register
0x01C0 812C	0x01C0 852C	0x01E3 812C	ERRDET	Error Details Register
0x01C0 8130	0x01C0 8530	0x01E3 8130	ERRCMD	Error Interrupt Command Register
0x01C0 8140	0x01C0 8540	0x01E3 8140	RDRATE	Read Command Rate Register
0x01C0 8240	0x01C0 8640	0x01E3 8240	SAOPT	Source Active Options Register
0x01C0 8244	0x01C0 8644	0x01E3 8244	SASRC	Source Active Source Address Register
0x01C0 8248	0x01C0 8648	0x01E3 8248	SACNT	Source Active Count Register
0x01C0 824C	0x01C0 864C	0x01E3 824C	SADST	Source Active Destination Address Register
0x01C0 8250	0x01C0 8650	0x01E3 8250	SABIDX	Source Active B-Index Register
0x01C0 8254	0x01C0 8654	0x01E3 8254	SAMPPRXY	Source Active Memory Protection Proxy Register
0x01C0 8258	0x01C0 8658	0x01E3 8258	SACNTRLD	Source Active Count Reload Register
0x01C0 825C	0x01C0 865C	0x01E3 825C	SASRCBREF	Source Active Source Address B-Reference Register
0x01C0 8260	0x01C0 8660	0x01E3 8260	SADSTBREF	Source Active Destination Address B-Reference Register
0x01C0 8280	0x01C0 8680	0x01E3 8280	DFCNTRLD	Destination FIFO Set Count Reload Register
0x01C0 8284	0x01C0 8684	0x01E3 8284	DFSRCBREF	Destination FIFO Set Source Address B-Reference Register
0x01C0 8288	0x01C0 8688	0x01E3 8288	DFDSTBREF	Destination FIFO Set Destination Address B-Reference Register
0x01C0 8300	0x01C0 8700	0x01E3 8300	DFOPT0	Destination FIFO Options Register 0
0x01C0 8304	0x01C0 8704	0x01E3 8304	DFSRC0	Destination FIFO Source Address Register 0
0x01C0 8308	0x01C0 8708	0x01E3 8308	DFCNT0	Destination FIFO Count Register 0
0x01C0 830C	0x01C0 870C	0x01E3 830C	DFDST0	Destination FIFO Destination Address Register 0
0x01C0 8310	0x01C0 8710	0x01E3 8310	DFBIDX0	Destination FIFO B-Index Register 0
0x01C0 8314	0x01C0 8714	0x01E3 8314	DFMPPRXY0	Destination FIFO Memory Protection Proxy Register 0
0x01C0 8340	0x01C0 8740	0x01E3 8340	DFOPT1	Destination FIFO Options Register 1
0x01C0 8344	0x01C0 8744	0x01E3 8344	DFSRC1	Destination FIFO Source Address Register 1
0x01C0 8348	0x01C0 8748	0x01E3 8348	DFCNT1	Destination FIFO Count Register 1
0x01C0 834C	0x01C0 874C	0x01E3 834C	DFDST1	Destination FIFO Destination Address Register 1
0x01C0 8350	0x01C0 8750	0x01E3 8350	DFBIDX1	Destination FIFO B-Index Register 1
0x01C0 8354	0x01C0 8754	0x01E3 8354	DFMPPRXY1	Destination FIFO Memory Protection Proxy Register 1
0x01C0 8380	0x01C0 8780	0x01E3 8380	DFOPT2	Destination FIFO Options Register 2
0x01C0 8384	0x01C0 8784	0x01E3 8384	DFSRC2	Destination FIFO Source Address Register 2
0x01C0 8388	0x01C0 8788	0x01E3 8388	DFCNT2	Destination FIFO Count Register 2
0x01C0 838C	0x01C0 878C	0x01E3 838C	DFDST2	Destination FIFO Destination Address Register 2
0x01C0 8390	0x01C0 8790	0x01E3 8390	DFBIDX2	Destination FIFO B-Index Register 2
0x01C0 8394	0x01C0 8794	0x01E3 8394	DFMPPRXY2	Destination FIFO Memory Protection Proxy Register 2
0x01C0 83C0	0x01C0 87C0	0x01E3 83C0	DFOPT3	Destination FIFO Options Register 3
0x01C0 83C4	0x01C0 87C4	0x01E3 83C4	DFSRC3	Destination FIFO Source Address Register 3
0x01C0 83C8	0x01C0 87C8	0x01E3 83C8	DFCNT3	Destination FIFO Count Register 3
0x01C0 83CC	0x01C0 87CC	0x01E3 83CC	DFDST3	Destination FIFO Destination Address Register 3
0x01C0 83D0	0x01C0 87D0	0x01E3 83D0	DFBIDX3	Destination FIFO B-Index Register 3
0x01C0 83D4	0x01C0 87D4	0x01E3 83D4	DFMPPRXY3	Destination FIFO Memory Protection Proxy Register 3

Table 6-15 shows an abbreviation of the set of registers which make up the parameter set for each of 128 EDMA3 events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-16 shows the parameter set entry registers with relative memory address locations within each of the parameter sets.

Table 6-15 EDMA3 Parameter Set RAM

EDMA3_0 Channel Controller 0 BYTE ADDRESS RANGE	EDMA3_1 Channel Controller 0 BYTE ADDRESS RANGE	DESCRIPTION
0x01C0 4000 - 0x01C0 401F	0x01E3 4000 - 0x01E3 401F	Parameters Set 0 (8 32-bit words)
0x01C0 4020 - 0x01C0 403F	0x01E3 4020 - 0x01E3 403F	Parameters Set 1 (8 32-bit words)
0x01C0 4040 - 0x01CC0 405F	0x01E3 4040 - 0x01CE3 405F	Parameters Set 2 (8 32-bit words)
0x01C0 4060 - 0x01C0 407F	0x01E3 4060 - 0x01E3 407F	Parameters Set 3 (8 32-bit words)
0x01C0 4080 - 0x01C0 409F	0x01E3 4080 - 0x01E3 409F	Parameters Set 4 (8 32-bit words)
0x01C0 40A0 - 0x01C0 40BF	0x01E3 40A0 - 0x01E3 40BF	Parameters Set 5 (8 32-bit words)
...	...	...
0x01C0 4FC0 - 0x01C0 4FDF	0x01E3 4FC0 - 0x01E3 4FDF	Parameters Set 126 (8 32-bit words)
0x01C0 4FE0 - 0x01C0 4FFF	0x01E3 4FE0 - 0x01E3 4FFF	Parameters Set 127 (8 32-bit words)

Table 6-16 Parameter Set Entries

OFFSET BYTE ADDRESS WITHIN THE PARAMETER SET	ACRONYM	PARAMETER ENTRY
0x0000	OPT	Option
0x0004	SRC	Source Address
0x0008	A_B_CNT	A Count, B Count
0x000C	DST	Destination Address
0x0010	SRC_DST_BIDX	Source B Index, Destination B Index
0x0014	LINK_BCNTRLD	Link Address, B Count Reload
0x0018	SRC_DST_CIDX	Source C Index, Destination C Index
0x001C	CCNT	C Count

6.10 External Memory Interface A (EMIFA)

EMIFA is one of two external memory interfaces supported on the device. It is primarily intended to support asynchronous memory types, such as NAND and NOR flash and Asynchronous SRAM. However on this device, EMIFA also provides a secondary interface to SDRAM.

6.10.1 EMIFA Asynchronous Memory Support

EMIFA supports asynchronous:

SRAM memories
NAND Flash memories
NOR Flash memories

The EMIFA data bus width is up to 16-bits.The device supports up to 23 address lines and two external wait/interrupt inputs. Up to four asynchronous chip selects are supported by EMIFA (EMA_CS[5:2]).

Each chip select has the following individually programmable attributes:

Data Bus Width
Read cycle timings: setup, hold, strobe
Write cycle timings: setup, hold, strobe
Bus turn around time
Extended Wait Option With Programmable Timeout
Select Strobe Option
NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes.

6.10.2 EMIFA Synchronous DRAM Memory Support

The device supports 16-bit SDRAM in addition to the asynchronous memories listed in Section 6.10.1. It has a single SDRAM chip select (EMA_CS[0]). SDRAM configurations that are supported are:

One, Two, and Four Bank SDRAM devices
Devices with Eight, Nine, Ten, and Eleven Column Address
CAS Latency of two or three clock cycles
Sixteen Bit Data Bus Width

Additionally, the SDRAM interface of EMIFA supports placing the SDRAM in Self Refresh and Powerdown Modes. Self Refresh mode allows the SDRAM to be put into a low power state while still retaining memory contents; since the SDRAM will continue to refresh itself even without clocks from the device. Powerdown mode achieves even lower power, except the device must periodically wake the SDRAM up and issue refreshes if data retention is required.

Finally, note that the EMIFA does not support Mobile SDRAM devices.

Table 6-17 shows the supported SDRAM configurations for EMIFA.

Table 6-17 EMIFA Supported SDRAM Configurations⁽¹⁾

SDRAM Memory Data Bus Width (bits)	Number of Memories	EMIFA Data Bus Size (bits)	Rows	Columns	Banks	Total Memory (Mbits)	Total Memory (Mbytes)	Memory Density (Mbits)
	1	16	16	8	1	256	32	256
	1	16	16	8	2	512	64	512
	1	16	16	8	4	1024	128	1024
	1	16	16	9	1	512	64	512
	1	16	16	9	2	1024	128	1024
16	1	16	16	9	4	2048	256	2048
	1	16	16	10	1	1024	128	1024
	1	16	16	10	2	2048	256	2048
	1	16	16	10	4	4096	512	4096
	1	16	16	11	1	2048	256	2048
	1	16	16	11	2	4096	512	4096
	1	16	15	11	4	4096	512	4096
	2	16	16	8	1	256	32	128
	2	16	16	8	2	512	64	256
	2	16	16	8	4	1024	128	512
	2	16	16	9	1	512	64	256
	2	16	16	9	2	1024	128	512
8	2	16	16	9	4	2048	256	1024
	2	16	16	10	1	1024	128	512
	2	16	16	10	2	2048	256	1024
	2	16	16	10	4	4096	512	2048
	2	16	16	11	1	2048	256	1024
	2	16	16	11	2	4096	512	2048
	2	16	15	11	4	4096	512	2048

(1) The shaded cells indicate configurations that are possible on the EMIFA interface but as of this writing SDRAM memories capable of supporting these densities are not available in the market.

6.10.3 EMIFA SDRAM Loading Limitations

EMIFA supports SDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads. Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be confirmed by board simulation using IBIS models.

6.10.4 EMIFA Connection Examples

Figure 6-10 illustrates an example of how SDRAM, NOR, and NAND flash devices might be connected to EMIFA simultaneously. The SDRAM chip select must be EMA_CS[0]. Note that the NOR flash is connected to EMA_CS[2] and the NAND flash is connected to EMA_CS[3] in this example. Note that any type of asynchronous memory may be connected to EMA_CS[5:2].

The on-chip bootloader makes some assumptions on which chip select the contains the boot image, and this depends on the boot mode. For NOR boot mode; the on-chip bootloader requires that the image be stored in NOR flash on EMA_CS[2]. For NAND boot mode, the bootloader requires that the boot image is stored in NAND flash on EMA_CS[3]. It is always possible to have the image span multiple chip selects, but this must be supported by second stage boot code stored in the external flash.

A likely use case with more than one EMIFA chip select used for NAND flash is illustrated in Figure 6-11. This figure shows how two multiplane NAND flash devices with two chip selects each would connect to the EMIFA. In this case if NAND is the boot memory, then the boot image needs to be stored in the NAND area selected by EMA_CS[3]. Part of the application image could spill over into the NAND regions selected by other EMIFA chip selects; but would rely on the code stored in the EMA_CS[3] area to bootload it.

Figure 6-10 Connection Diagram: SDRAM, NOR, NAND

Figure 6-11 EMIFA Connection Diagram: Multiple NAND Flash Planes

6.10.5 External Memory Interface Register Descriptions

Table 6-18 External Memory Interface (EMIFA) Registers

BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x6800 0000	MIDR	Module ID Register
0x6800 0004	AWCC	Asynchronous Wait Cycle Configuration Register
0x6800 0008	SDCR	SDRAM Configuration Register
0x6800 000C	SDRCR	SDRAM Refresh Control Register
0x6800 0010	CE2CFG	Asynchronous 1 Configuration Register
0x6800 0014	CE3CFG	Asynchronous 2 Configuration Register
0x6800 0018	CE4CFG	Asynchronous 3 Configuration Register
0x6800 001C	CE5CFG	Asynchronous 4 Configuration Register
0x6800 0020	SDTIMR	SDRAM Timing Register
0x6800 003C	SDSRETR	SDRAM Self Refresh Exit Timing Register
0x6800 0040	INTRAW	EMIFA Interrupt Raw Register
0x6800 0044	INTMSK	EMIFA Interrupt Mask Register
0x6800 0048	INTMSKSET	EMIFA Interrupt Mask Set Register
0x6800 004C	INTMSKCLR	EMIFA Interrupt Mask Clear Register
0x6800 0060	NANDFCR	NAND Flash Control Register
0x6800 0064	NANDFSR	NAND Flash Status Register
0x6800 0070	NANDF1ECC	NAND Flash 1 ECC Register (CS2 Space)
0x6800 0074	NANDF2ECC	NAND Flash 2 ECC Register (CS3 Space)
0x6800 0078	NANDF3ECC	NAND Flash 3 ECC Register (CS4 Space)
0x6800 007C	NANDF4ECC	NAND Flash 4 ECC Register (CS5 Space)
0x6800 00BC	NAND4BITECCLOAD	NAND Flash 4-Bit ECC Load Register
0x6800 00C0	NAND4BITECC1	NAND Flash 4-Bit ECC Register 1
0x6800 00C4	NAND4BITECC2	NAND Flash 4-Bit ECC Register 2
0x6800 00C8	NAND4BITECC3	NAND Flash 4-Bit ECC Register 3
0x6800 00CC	NAND4BITECC4	NAND Flash 4-Bit ECC Register 4
0x6800 00D0	NANDERRADD1	NAND Flash 4-Bit ECC Error Address Register 1
0x6800 00D4	NANDERRADD2	NAND Flash 4-Bit ECC Error Address Register 2
0x6800 00D8	NANDERRVAL1	NAND Flash 4-Bit ECC Error Value Register 1
0x6800 00DC	NANDERRVAL2	NAND Flash 4-Bit ECC Error Value Register 2

6.10.6 EMIFA Electrical Data/Timing

Table 6-19 through Table 6-22 assume testing over recommended operating conditions.

Table 6-19 Timing Requirements for EMIFA SDRAM Interface

NO.			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
19	t_{su(EMA_DV-EM_CLKH)}	Input setup time, read data valid on EMA_D[15:0] before EMA_CLK rising	2		3		3		ns
20	t_h(CLKH-DIV)	Input hold time, read data valid on EMA_D[15:0] after EMA_CLK rising	1.6		1.6		1.6		ns

Table 6-20 Switching Characteristics for EMIFA SDRAM Interface

NO.	PARAMETER		1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER		MIN	MAX	MIN	MAX	MIN	MAX	UNIT
1	t_c(CLK)	Cycle time, EMIF clock EMA_CLK	10		15		20		ns
2	t_w(CLK)	Pulse width, EMIF clock EMA_CLK high or low	3		5		8		ns
3	t_d(CLKH-CSV)	Delay time, EMA_CLK rising to EMA_CS[0] valid		7		9.5		13	ns
4	t_{oh(CLKH-CSIV)}	Output hold time, EMA_CLK rising to EMA_CS[0] invalid	1		1		1		ns
5	t_d(CLKH-DQMV)	Delay time, EMA_CLK rising to EMA_WE_DQM[1:0] valid		7		9.5		13	ns
6	t_{oh(CLKH-DQMIV)}	Output hold time, EMA_CLK rising to EMA_WE_DQM[1:0] invalid	1		1		1		ns
7	t_d(CLKH-AV)	Delay time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0] valid		7		9.5		13	ns
8	t_oh(CLKH-AIV)	Output hold time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0] invalid	1		1		1		ns
9	t_d(CLKH-DV)	Delay time, EMA_CLK rising to EMA_D[15:0] valid		7		9.5		13	ns
10	t_oh(CLKH-DIV)	Output hold time, EMA_CLK rising to EMA_D[15:0] invalid	1		1		1		ns
11	t_d(CLKH-RASV)	Delay time, EMA_CLK rising to EMA_RAS valid		7		9.5		13	ns
12	t_{oh(CLKH-RASIV)}	Output hold time, EMA_CLK rising to EMA_RAS invalid	1		1		1		ns
13	t_d(CLKH-CASV)	Delay time, EMA_CLK rising to EMA_CAS valid		7		9.5		13	ns
14	t_{oh(CLKH-CASIV)}	Output hold time, EMA_CLK rising to EMA_CAS invalid	1		1		1		ns
15	t_d(CLKH-WEV)	Delay time, EMA_CLK rising to EMA_WE valid		7		9.5		13	ns
16	t_{oh(CLKH-WEIV)}	Output hold time, EMA_CLK rising to EMA_WE invalid	1		1		1		ns
17	t_{dis(CLKH-DHZ)}	Delay time, EMA_CLK rising to EMA_D[15:0] tri-stated		7		9.5		13	ns
18	t_{ena(CLKH-DLZ)}	Output hold time, EMA_CLK rising to EMA_D[15:0] driving	1		1		1		ns

Figure 6-12 EMIFA Basic SDRAM Write Operation

Figure 6-13 EMIFA Basic SDRAM Read Operation

Table 6-21 Timing Requirements for EMIFA Asynchronous Memory Interface ⁽¹⁾

NO.			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
		READS and WRITES
E	t_c(CLK)	Cycle time, EMIFA module clock	6.75		13.33		20		ns
2	t_{w(EM_WAIT)}	Pulse duration, EM_WAIT assertion and deassertion	2E		2E		2E		ns
		READS
12	t_{su(EMDV-EMOEH)}	Setup time, EM_D[15:0] valid before EM_OE high	3		5		7		ns
13	t_{h(EMOEH-EMDIV)}	Hold time, EM_D[15:0] valid after EM_OE high	0		0		0		ns
14	t_su _{(EMOEL-EMWAIT)}	Setup Time, EM_WAIT asserted before end of Strobe Phase⁽²⁾	4E+3		4E+3		4E+3		ns
		WRITES
28	t_su _{(EMWEL-EMWAIT)}	Setup Time, EM_WAIT asserted before end of Strobe Phase⁽²⁾	4E+3		4E+3		4E+3		ns

(1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz, E=10ns

(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended wait states. Figure 6-16 and Figure 6-17 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles.

Table 6-22 Switching Characteristics for EMIFA Asynchronous Memory Interface ⁽¹⁾ ⁽²⁾ ⁽³⁾

NO.	PARAMETER		1.3V, 1.2V, 1.1V, 1.0V			UNIT
NO.	PARAMETER		MIN	Nom	MAX	UNIT
READS and WRITES
1	t_{d(TURNAROUND)}	Turn around time	(TA)*E - 3	(TA)*E	(TA)*E + 3	ns
READS
3	t_c(EMRCYCLE)	EMIF read cycle time (EW = 0)	(RS+RST+RH)*E - 3	(RS+RST+RH)*E	(RS+RST+RH)*E + 3	ns
3	t_c(EMRCYCLE)	EMIF read cycle time (EW = 1)	(RS+RST+RH+EWC)*E - 3	(RS+RST+RH+EWC)*E	(RS+RST+RH+EWC)*E + 3	ns
4	t_{su(EMCEL-EMOEL)}	Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 0)	(RS)*E-3	(RS)*E	(RS)*E+3	ns
4	t_{su(EMCEL-EMOEL)}	Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 1)	-3	0	+3	ns
5	t_{h(EMOEH-EMCEH)}	Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 0)	(RH)*E - 3	(RH)*E	(RH)*E + 3	ns
5	t_{h(EMOEH-EMCEH)}	Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 1)	-3	0	+3	ns
6	t_{su(EMBAV-EMOEL)}	Output setup time, EMA_BA[1:0] valid to EMA_OE low	(RS)*E-3	(RS)*E	(RS)*E+3	ns
7	t_{h(EMOEH-EMBAIV)}	Output hold time, EMA_OE high to EMA_BA[1:0] invalid	(RH)*E-3	(RH)*E	(RH)*E+3	ns
8	t_{su(EMBAV-EMOEL)}	Output setup time, EMA_A[13:0] valid to EMA_OE low	(RS)*E-3	(RS)*E	(RS)*E+3	ns
9	t_{h(EMOEH-EMAIV)}	Output hold time, EMA_OE high to EMA_A[13:0] invalid	(RH)*E-3	(RH)*E	(RH)*E+3	ns
10	t_w(EMOEL)	EMA_OE active low width (EW = 0)	(RST)*E-3	(RST)*E	(RST)*E+3	ns
10	t_w(EMOEL)	EMA_OE active low width (EW = 1)	(RST+EWC)*E-3	(RST+EWC)*E	(RST+EWC)*E+3	ns
11	t_{d(EMWAITH-EMOEH)}	Delay time from EMA_WAIT deasserted to EMA_OE high	3E-3	4E	4E+3	ns
28	t_{su(EMARW-EMOEL)}	Output setup time, EMA_A_RW valid to EMA_OE low	(RS)*E-3	(RS)*E	(RS)*E+3	ns
29	t_{h(EMOEH-EMARW)}	Output hold time, EMA_OE high to EMA_A_RW invalid	(RH)*E-3	(RH)*E	(RH)*E+3	ns
WRITES
15	t_c(EMWCYCLE)	EMIF write cycle time (EW = 0)	(WS+WST+WH)*E-3	(WS+WST+WH)*E	(WS+WST+WH)*E+3	ns
15	t_c(EMWCYCLE)	EMIF write cycle time (EW = 1)	(WS+WST+WH+EWC)*E - 3	(WS+WST+WH+EWC)*E	(WS+WST+WH+EWC)*E + 3	ns
16	t_{su(EMCEL-EMWEL)}	Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 0)	(WS)*E - 3	(WS)*E	(WS)*E + 3	ns
16	t_{su(EMCEL-EMWEL)}	Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 1)	-3	0	+3	ns
17	t_{h(EMWEH-EMCEH)}	Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 0)	(WH)*E-3	(WH)*E	(WH)*E+3	ns
17	t_{h(EMWEH-EMCEH)}	Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 1)	-3	0	+3	ns
18	t_{su(EMDQMV-EMWEL)}	Output setup time, EMA_BA[1:0] valid to EMA_WE low	(WS)*E-3	(WS)*E	(WS)*E+3	ns
19	t_{h(EMWEH-EMDQMIV)}	Output hold time, EMA_WE high to EMA_BA[1:0] invalid	(WH)*E-3	(WH)*E	(WH)*E+3	ns
20	t_{su(EMBAV-EMWEL)}	Output setup time, EMA_BA[1:0] valid to EMA_WE low	(WS)*E-3	(WS)*E	(WS)*E+3	ns
21	t_{h(EMWEH-EMBAIV)}	Output hold time, EMA_WE high to EMA_BA[1:0] invalid	(WH)*E-3	(WH)*E	(WH)*E+3	ns
22	t_{su(EMAV-EMWEL)}	Output setup time, EMA_A[13:0] valid to EMA_WE low	(WS)*E-3	(WS)*E	(WS)*E+3	ns
23	t_{h(EMWEH-EMAIV)}	Output hold time, EMA_WE high to EMA_A[13:0] invalid	(WH)*E-3	(WH)*E	(WH)*E+3	ns
24	t_w(EMWEL)	EMA_WE active low width (EW = 0)	(WST)*E-3	(WST)*E	(WST)*E+3	ns
24	t_w(EMWEL)	EMA_WE active low width (EW = 1)	(WST+EWC)*E-3	(WST+EWC)*E	(WST+EWC)*E+3	ns
25	t_{d(EMWAITH-EMWEH)}	Delay time from EMA_WAIT deasserted to EMA_WE high	3E-3	4E	4E+3	ns
26	t_{su(EMDV-EMWEL)}	Output setup time, EMA_D[15:0] valid to EMA_WE low	(WS)*E-3	(WS)*E	(WS)*E+3	ns
27	t_{h(EMWEH-EMDIV)}	Output hold time, EMA_WE high to EMA_D[15:0] invalid	(WH)*E-3	(WH)*E	(WH)*E+3	ns
30	t_{su(EMARW-EMWEL)}	Output setup time, EMA_A_RW valid to EMA_WE low	(WS)*E-3	(WS)*E	(WS)*E+3	ns
31	t_{h(EMWEH-EMARW)}	Output hold time, EMA_WE high to EMA_A_RW invalid	(WH)*E-3	(WH)*E	(WH)*E+3	ns

(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1], WH[8-1], and MEW[1-256].

(2) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz, E=10ns.

(3) EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.

Figure 6-14 Asynchronous Memory Read Timing for EMIFA

Figure 6-15 Asynchronous Memory Write Timing for EMIFA

Figure 6-16 EMA_WAIT Read Timing Requirements

Figure 6-17 EMA_WAIT Write Timing Requirements

6.11 DDR2/mDDR Memory Controller

The DDR2/mDDR Memory Controller is a dedicated interface to DDR2/mDDR SDRAM. It supports JESD79-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices.

The DDR2/mDDR Memory Controller support the following features:

JESD79-2A standard compliant DDR2 SDRAM
Mobile DDR SDRAM
256 MByte memory space for DDR2
256 MByte memory space for mDDR
CAS latencies:
- DDR2: 2, 3, 4 and 5
- mDDR: 2 and 3
Internal banks:
- DDR2: 1, 2, 4 and 8
- mDDR:1, 2 and 4
Burst length: 8
Burst type: sequential
1 chip select (CS) signal
Page sizes: 256, 512, 1024, and 2048
SDRAM autoinitialization
Self-refresh mode
Partial array self-refresh (for mDDR)
Power down mode
Prioritized refresh
Programmable refresh rate and backlog counter
Programmable timing parameters
Little endian

6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing

Table 6-23 Switching Characteristics Over Recommended Operating Conditions for DDR2/mDDR Memory Controller

No.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
No.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
1	t_{c(DDR_CLK)}	Cycle time, DDR_CLKP / DDR_CLKN	DDR2	125	156	125	150	—⁽¹⁾	—⁽¹⁾	MHz
1	t_{c(DDR_CLK)}	Cycle time, DDR_CLKP / DDR_CLKN	mDDR	105	150	100	133	95	133	MHz

(1) DDR2 is not supported at this voltage operating point.

6.11.2 DDR2/mDDR Memory Controller Register Description(s)

Table 6-24 DDR2/mDDR Memory Controller Registers

BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0xB000 0000	REVID	Revision ID Register
0xB000 0004	SDRSTAT	SDRAM Status Register
0xB000 0008	SDCR	SDRAM Configuration Register
0xB000 000C	SDRCR	SDRAM Refresh Control Register
0xB000 0010	SDTIMR1	SDRAM Timing Register 1
0xB000 0014	SDTIMR2	SDRAM Timing Register 2
0xB000 001C	SDCR2	SDRAM Configuration Register 2
0xB000 0020	PBBPR	Peripheral Bus Burst Priority Register
0xB000 0040	PC1	Performance Counter 1 Registers
0xB000 0044	PC2	Performance Counter 2 Register
0xB000 0048	PCC	Performance Counter Configuration Register
0xB000 004C	PCMRS	Performance Counter Master Region Select Register
0xB000 0050	PCT	Performance Counter Time Register
0xB000 00C0	IRR	Interrupt Raw Register
0xB000 00C4	IMR	Interrupt Mask Register
0xB000 00C8	IMSR	Interrupt Mask Set Register
0xB000 00CC	IMCR	Interrupt Mask Clear Register
0xB000 00E4	DRPYC1R	DDR PHY Control Register 1
0x01E2 C000	VTPIO_CTL	VTP IO Control Register

6.11.3 DDR2/mDDR Interface

This section provides the timing specification for the DDR2/mDDR interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR memory system without the need for a complex timing closure process. For more information regarding guidelines for using this DDR2/mDDR specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0).

6.11.3.1 DDR2/mDDR Interface Schematic

Figure 6-18 shows the DDR2/mDDR interface schematic for a single-memory DDR2/mDDR system. The dual-memory system shown in Figure 6-19. Pin numbers for the device can be obtained from the pin description section.

1. See Figure 6-25 for DQGATE routing specifications.

2. For DDR2, one of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. For mDDR, these capacitors can be eliminated completely.

3. VREF applies in the case of DDR2 memories. For mDDR, the DDR_VREF pin still needs to be connected to the divider circuit.

Figure 6-18 DDR2/mDDR Single-Memory High Level Schematic

1. See Figure 6-25 for DQGATE routing specifications.

2. For DDR2, one of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. For mDDR, these capacitors can be eliminated completely.

3. VREF applies in the case of DDR2 memories. For mDDR, the DDR_VREF pin still needs to be connected to the divider circuit.

Figure 6-19 DDR2/mDDR Dual-Memory High Level Schematic

6.11.3.2 Compatible JEDEC DDR2/mDDR Devices

Table 6-25 shows the parameters of the JEDEC DDR2/mDDR devices that are compatible with this interface. Generally, the DDR2/mDDR interface is compatible with x16 DDR2-400/mDDR-200 speed grade DDR2/mDDR devices.

The device also supports JEDEC DDR2/mDDR x8 devices in the dual chip configuration. In this case, one chip supplies the upper byte and the second chip supplies the lower byte. Addresses and most control signals are shared just like regular dual chip memory configurations.

Table 6-25 Compatible JEDEC DDR2/mDDR Devices

NO.	PARAMETER	MIN	MAX	UNIT
1	JEDEC DDR2/mDDR Device Speed Grade⁽¹⁾	DDR2-400/mDDR-200
2	JEDEC DDR2/mDDR Device Bit Width	x8	x16	Bits
3	JEDEC DDR2/mDDR Device Count⁽²⁾	1	2	Devices

(1) Higher DDR2/mDDR speed grades are supported due to inherent JEDEC DDR2/mDDR backwards compatibility.

(2) Supported configurations are one 16-bit DDR2/mDDR memory or two 8-bit DDR2/mDDR memories

6.11.3.3 PCB Stackup

The minimum stackup required for routing the device is a six layer stack as shown in Table 6-26. Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB footprint.Complete stack up specifications are provided in Table 6-27.

Table 6-26 Device Minimum PCB Stack Up

LAYER	TYPE	DESCRIPTION
1	Signal	Top Routing Mostly Horizontal
2	Plane	Ground
3	Plane	Power
4	Signal	Internal Routing
5	Plane	Ground
6	Signal	Bottom Routing Mostly Vertical

Table 6-27 PCB Stack Up Specifications

NO.	PARAMETER	MIN	TYP	MAX	UNIT
1	PCB Routing/Plane Layers	6
2	Signal Routing Layers	3
3	Full ground layers under DDR2/mDDR routing region	2
4	Number of ground plane cuts allowed within DDR routing region			0
5	Number of ground reference planes required for each DDR2/mDDR routing layer	1
6	Number of layers between DDR2/mDDR routing layer and reference ground plane			0
7	PCB Routing Feature Size		4		Mils
8	PCB Trace Width w		4		Mils
8	PCB BGA escape via pad size		18		Mils
9	PCB BGA escape via hole size		8		Mils
10	Device BGA pad size⁽¹⁾
11	DDR2/mDDR Device BGA pad size⁽²⁾
12	Single Ended Impedance, Zo	50		75	Ω
13	Impedance Control⁽³⁾	Z-5	Z	Z+5	Ω

(1) Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for device BGA pad size.

(2) Please refer to the DDR2/mDDR device manufacturer documentation for the DDR2/mDDR device BGA pad size.

(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.

6.11.3.4 Placement

Figure 6-19 shows the required placement for the device as well as the DDR2/mDDR devices. The dimensions for Figure 6-20 are defined in Table 6-28. The placement does not restrict the side of the PCB that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory DDR2/mDDR systems, the second DDR2/mDDR device is omitted from the placement.

Figure 6-20 C6746 and DDR2/mDDR Device Placement

Table 6-28 Placement Specifications⁽¹⁾⁽²⁾

NO.	PARAMETER	MIN	MAX	UNIT
1	X		1750	Mils
2	Y		1280	Mils
3	Y Offset	⁽³⁾	650	Mils
4	Clearance from non-DDR2/mDDR signal to DDR2/mDDR Keepout Region⁽⁴⁾	4		w⁽⁵⁾

(1) See Figure 6-20 for dimension definitions.

(2) Measurements from center of device to center of DDR2/mDDR device.

(3) For single memory systems it is recommended that Y Offset be as small as possible.

(4) Non-DDR2/mDDR signals allowed within DDR2/mDDR keepout region provided they are separated from DDR2/mDDR routing layers by a ground plane.

(5) w = PCB trace width as defined in Table 6-27.

6.11.3.5 DDR2/mDDR Keep Out Region

The region of the PCB used for the DDR2/mDDR circuitry must be isolated from other signals. The DDR2/mDDR keep out region is defined for this purpose and is shown in Figure 6-21. The size of this region varies with the placement and DDR routing. Additional clearances required for the keep out region are shown in Table 6-28.

Figure 6-21 DDR2/mDDR Keepout Region

6.11.3.6 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR2/mDDR and other circuitry. Table 6-29 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the DSP and DDR2/mDDR interfaces. Additional bulk bypass capacitance may be needed for other circuitry.

Table 6-29 Bulk Bypass Capacitors

NO.	PARAMETER	MIN	UNIT
1	DDR_DVDD18 Supply Bulk Bypass Capacitor Count⁽¹⁾	3	Devices
2	DDR_DVDD18 Supply Bulk Bypass Total Capacitance	30	μF
3	DDR#1 Bulk Bypass Capacitor Count⁽¹⁾	1	Devices
4	DDR#1 Bulk Bypass Total Capacitance	22	μF
5	DDR#2 Bulk Bypass Capacitor Count⁽¹⁾⁽²⁾	1	Devices
6	DDR#2 Bulk Bypass Total Capacitance⁽²⁾	22	μF

(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed (HS) bypass caps.

(2) Only used on dual-memory systems.

6.11.3.7 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critical for proper DDR2/mDDR interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass cap, DSP/DDR2/mDDR power, and DSP/DDR2/mDDR ground connections. Table 6-30 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB.

Table 6-30 High-Speed Bypass Capacitors

NO.	PARAMETER	MIN	MAX	UNIT
1	HS Bypass Capacitor Package Size⁽¹⁾		0402	10 Mils
2	Distance from HS bypass capacitor to device being bypassed		250	Mils
3	Number of connection vias for each HS bypass capacitor	2⁽⁴⁾		Vias
4	Trace length from bypass capacitor contact to connection via	1	30	Mils
5	Number of connection vias for each DDR2/mDDR device power or ground balls	1		Vias
6	Trace length from DDR2/mDDR device power ball to connection via		35	Mils
7	DDR_DVDD18 Supply HS Bypass Capacitor Count⁽²⁾	10		Devices
8	DDR_DVDD18 Supply HS Bypass Capacitor Total Capacitance	0.6		μF
9	DDR#1 HS Bypass Capacitor Count⁽²⁾	8		Devices
10	DDR#1 HS Bypass Capacitor Total Capacitance	0.4		μF
11	DDR#2 HS Bypass Capacitor Count⁽²⁾⁽³⁾	8		Devices
12	DDR#2 HS Bypass Capacitor Total Capacitance⁽³⁾	0.4		μF

(1) LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor

(2) These devices should be placed as close as possible to the device being bypassed.

(3) Only used on dual-memory systems.

(4) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.

6.11.3.8 Net Classes

Table 6-31 lists the clock net classes for the DDR2/mDDR interface. Table 6-32 lists the signal net classes, and associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes are used for the termination and routing rules that follow.

Table 6-31 Clock Net Class Definitions

CLOCK NET CLASS	DSP PIN NAMES
CK	DDR_CLKP / DDR_CLKN
DQS0	DDR_DQS[0]
DQS1	DDR_DQS[1]

Table 6-32 Signal Net Class Definitions

SIGNAL NET CLASS	ASSOCIATED CLOCK NET CLASS	DSP PIN NAMES
ADDR_CTRL	CK	DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE, DDR_CKE
D0	DQS0	DDR_D[7:0], DDR_DQM0
D1	DQS1	DDR_D[15:8], DDR_DQM1
DQGATE	CK, DQS0, DQS1	DDR_DQGATE0, DDR_DQGATE1

6.11.3.9 DDR2/mDDR Signal Termination

No terminations of any kind are required in order to meet signal integrity and overshoot requirements. Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only type permitted. Table 6-33 shows the specifications for the series terminators.

Table 6-33 DDR2/mDDR Signal Terminations⁽¹⁾⁽²⁾⁽³⁾

NO.	PARAMETER	TYP	MAX	UNIT
1	CK Net Class		10	Ω
2	ADDR_CTRL Net Class	22	Zo	Ω
3	Data Byte Net Classes (DQS[0], DQS[1], D0, D1)⁽⁴⁾	22	Zo	Ω
4	DQGATE Net Class (DQGATE)	10	Zo	Ω

(1) Only series termination is permitted, parallel or SST specifically disallowed.

(2) Terminator values larger than typical only recommended to address EMI issues.

(3) Termination value should be uniform across net class.

(4) When no termination is used on data lines (0 Ω), the DDR2/mDDR devices must be programmed to operate in 60% strength mode.

6.11.3.10 VREF Routing

VREF is used as a reference by the input buffers of the DDR2/mDDR memories as well as the C6746 . VREF is intended to be half the DDR2/mDDR power supply voltage and should be created using a resistive divider as shown in Figure 6-18. Other methods of creating VREF are not recommended. Figure 6-22 shows the layout guidelines for VREF.

Figure 6-22 VREF Routing and Topology

6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing

Figure 6-23 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized.

Figure 6-23 CK and ADDR_CTRL Routing and Topology

Table 6-34 CK and ADDR_CTRL Routing Specification

NO.	PARAMETER	MIN	TYP	MAX	UNIT
1	Center to Center CK-CKN Spacing⁽³⁾			2w⁽⁴⁾
2	CK A to B/A to C Skew Length Mismatch⁽¹⁾			25	Mils
3	CK B to C Skew Length Mismatch			25	Mils
4	Center to center CK to other DDR2/mDDR trace spacing⁽³⁾	4w⁽⁴⁾
5	CK/ADDR_CTRL nominal trace length⁽²⁾	CACLM-50	CACLM	CACLM+50	Mils
6	ADDR_CTRL to CK Skew Length Mismatch			100	Mils
7	ADDR_CTRL to ADDR_CTRL Skew Length Mismatch			100	Mils
8	Center to center ADDR_CTRL to other DDR2/mDDR trace spacing⁽³⁾	4w⁽⁴⁾
9	Center to center ADDR_CTRL to other ADDR_CTRL trace spacing⁽³⁾	3w ⁽⁴⁾
10	ADDR_CTRL A to B/A to C Skew Length Mismatch⁽¹⁾			100	Mils
11	ADDR_CTRL B to C Skew Length Mismatch			100	Mils

(1) Series terminator, if used, should be located closest to device.

(2) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.

(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.

(4) w = PCB trace width as defined in Table 6-27.

Figure 6-24 shows the topology and routing for the DQS and D net class; the routes are point to point. Skew matching across bytes is not needed nor recommended.

Figure 6-24 DQS and D Routing and Topology

Table 6-35 DQS and D Routing Specification

NO.	PARAMETER	MIN	TYP	MAX	UNIT
1	Center to center DQS to other DDR2/mDDR trace spacing⁽⁴⁾	4w⁽⁶⁾
2	DQS/D nominal trace length⁽¹⁾⁽³⁾	DQLM-50	DQLM	DQLM+50	Mils
3	D to DQS Skew Length Mismatch⁽³⁾			100	Mils
4	D to D Skew Length Mismatch⁽³⁾			100	Mils
5	Center to center D to other DDR2/mDDR trace spacing⁽⁴⁾⁽⁵⁾	4w⁽⁶⁾
6	Center to Center D to other D trace spacing⁽⁴⁾⁽²⁾	3w⁽⁶⁾

(1) Series terminator, if used, should be located closest to DDR.

(2) DQLM is the longest Manhattan distance of each of the DQS and D net class.

(3) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte 1.

(4) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.

(5) D's from other DQS domains are considered other DDR2/mDDR trace.

(6) w = PCB trace width as defined in Table 6-27.

Figure 6-25 shows the routing for the DQGATE net class. Table 6-36 contains the routing specification.

Figure 6-25 DQGATE Routing

Table 6-36 DQGATE Routing Specification

NO.	PARAMETER	MIN	TYP	MAX	UNIT
1	DQGATE Length F		CKB0B⁽¹⁾
2	Center to center DQGATE to any other trace spacing	4w⁽³⁾
3	DQS/D nominal trace length	DQLM-50	DQLM	DQLM+50	Mils
4	DQGATE Skew⁽²⁾			100	Mils

(1) CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.

(2) Skew from CKB0B1

(3) w = PCB trace width as defined in Table 6-27.

6.11.3.12 DDR2/mDDR Boundary Scan Limitations

Due to DDR implementation and timing restrictions, it was not possible to place boundary scan cells between core logic and the IO like boundary scan cells for other IO. Instead, the boundary scan cells are tapped-off to the DDR PHY and there is the equivalent of a multiplexer inside the DDR PHY which selects between functional and boundary scan paths.

The implication for boundary scan is that the DDR pins will not support the SAMPLE function of the output enable cells on the DDR pins and this is a violation of IEEE 1149.1. Full EXTEST and PRELOAD capability is still available.

6.12 Memory Protection Units

The MPU performs memory protection checking. It receives requests from a bus master in the system and checks the address against the fixed and programmable regions to see if the access is allowed. If allowed, the transfer is passed unmodified to its output bus (to the targeted address). If the transfer is illegal (fails the protection check) then the MPU does not pass the transfer to the output bus but rather services the transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as well as generating an interrupt about the fault. The following features are supported by the MPU:

Provides memory protection for fixed and programmable address ranges.
Supports multiple programmable address region.
Supports secure and debug access privileges.
Supports read, write, and execute access privileges.
Supports privid(8) associations with ranges.
Generates an interrupt when there is a protection violation, and saves violating transfer parameters.
MMR access is also protected.

Table 6-37 MPU1 Configuration Registers

MPU1 BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01E1 4000	REVID	Revision ID
0x01E1 4004	CONFIG	Configuration
0x01E1 4010	IRAWSTAT	Interrupt raw status/set
0x01E1 4014	IENSTAT	Interrupt enable status/clear
0x01E1 4018	IENSET	Interrupt enable
0x01E1 401C	IENCLR	Interrupt enable clear
0x01E1 4020 - 0x01E1 41FF	-	Reserved
0x01E1 4200	PROG1_MPSAR	Programmable range 1, start address
0x01E1 4204	PROG1_MPEAR	Programmable range 1, end address
0x01E1 4208	PROG1_MPPA	Programmable range 1, memory page protection attributes
0x01E1 420C - 0x01E1 420F	-	Reserved
0x01E1 4210	PROG2_MPSAR	Programmable range 2, start address
0x01E1 4214	PROG2_MPEAR	Programmable range 2, end address
0x01E1 4218	PROG2_MPPA	Programmable range 2, memory page protection attributes
0x01E1 421C - 0x01E1 421F	-	Reserved
0x01E1 4220	PROG3_MPSAR	Programmable range 3, start address
0x01E1 4224	PROG3_MPEAR	Programmable range 3, end address
0x01E1 4228	PROG3_MPPA	Programmable range 3, memory page protection attributes
0x01E1 422C - 0x01E1 422F	-	Reserved
0x01E1 4230	PROG4_MPSAR	Programmable range 4, start address
0x01E1 4234	PROG4_MPEAR	Programmable range 4, end address
0x01E1 4238	PROG4_MPPA	Programmable range 4, memory page protection attributes
0x01E1 423C - 0x01E1 423F	-	Reserved
0x01E1 4240	PROG5_MPSAR	Programmable range 5, start address
0x01E1 4244	PROG5_MPEAR	Programmable range 5, end address
0x01E1 4248	PROG5_MPPA	Programmable range 5, memory page protection attributes
0x01E1 424C - 0x01E1 424F	-	Reserved
0x01E1 4250	PROG6_MPSAR	Programmable range 6, start address
0x01E1 4254	PROG6_MPEAR	Programmable range 6, end address
0x01E1 4258	PROG6_MPPA	Programmable range 6, memory page protection attributes
0x01E1 425C - 0x01E1 42FF	-	Reserved
0x01E1 4300	FLTADDRR	Fault address
0x01E1 4304	FLTSTAT	Fault status
0x01E1 4308	FLTCLR	Fault clear
0x01E1 430C - 0x01E1 4FFF	-	Reserved

Table 6-38 MPU2 Configuration Registers

MPU2 BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01E1 5000	REVID	Revision ID
0x01E1 5004	CONFIG	Configuration
0x01E1 5010	IRAWSTAT	Interrupt raw status/set
0x01E1 5014	IENSTAT	Interrupt enable status/clear
0x01E1 5018	IENSET	Interrupt enable
0x01E1 501C	IENCLR	Interrupt enable clear
0x01E1 5020 - 0x01E1 51FF	-	Reserved
0x01E1 5200	PROG1_MPSAR	Programmable range 1, start address
0x01E1 5204	PROG1_MPEAR	Programmable range 1, end address
0x01E1 5208	PROG1_MPPA	Programmable range 1, memory page protection attributes
0x01E1 520C - 0x01E1 520F	-	Reserved
0x01E1 5210	PROG2_MPSAR	Programmable range 2, start address
0x01E1 5214	PROG2_MPEAR	Programmable range 2, end address
0x01E1 5218	PROG2_MPPA	Programmable range 2, memory page protection attributes
0x01E1 521C - 0x01E1 521F	-	Reserved
0x01E1 5220	PROG3_MPSAR	Programmable range 3, start address
0x01E1 5224	PROG3_MPEAR	Programmable range 3, end address
0x01E1 5228	PROG3_MPPA	Programmable range 3, memory page protection attributes
0x01E1 522C - 0x01E1 522F	-	Reserved
0x01E1 5230	PROG4_MPSAR	Programmable range 4, start address
0x01E1 5234	PROG4_MPEAR	Programmable range 4, end address
0x01E1 5238	PROG4_MPPA	Programmable range 4, memory page protection attributes
0x01E1 523C - 0x01E1 523F	-	Reserved
0x01E1 5240	PROG5_MPSAR	Programmable range 5, start address
0x01E1 5244	PROG5_MPEAR	Programmable range 5, end address
0x01E1 5248	PROG5_MPPA	Programmable range 5, memory page protection attributes
0x01E1 524C - 0x01E1 524F	-	Reserved
0x01E1 5250	PROG6_MPSAR	Programmable range 6, start address
0x01E1 5254	PROG6_MPEAR	Programmable range 6, end address
0x01E1 5258	PROG6_MPPA	Programmable range 6, memory page protection attributes
0x01E1 525C - 0x01E1 525F	-	Reserved
0x01E1 5260	PROG7_MPSAR	Programmable range 7, start address
0x01E1 5264	PROG7_MPEAR	Programmable range 7, end address
0x01E1 5268	PROG7_MPPA	Programmable range 7, memory page protection attributes
0x01E1 526C - 0x01E1 526F	-	Reserved
0x01E1 5270	PROG8_MPSAR	Programmable range 8, start address
0x01E1 5274	PROG8_MPEAR	Programmable range 8, end address
0x01E1 5278	PROG8_MPPA	Programmable range 8, memory page protection attributes
0x01E1 527C - 0x01E1 527F	-	Reserved
0x01E1 5280	PROG9_MPSAR	Programmable range 9, start address
0x01E1 5284	PROG9_MPEAR	Programmable range 9, end address
0x01E1 5288	PROG9_MPPA	Programmable range 9, memory page protection attributes
0x01E1 528C - 0x01E1 528F	-	Reserved
0x01E1 5290	PROG10_MPSAR	Programmable range 10, start address
0x01E1 5294	PROG10_MPEAR	Programmable range 10, end address
0x01E1 5298	PROG10_MPPA	Programmable range 10, memory page protection attributes
0x01E1 529C - 0x01E1 529F	-	Reserved
0x01E1 52A0	PROG11_MPSAR	Programmable range 11, start address
0x01E1 52A4	PROG11_MPEAR	Programmable range 11, end address
0x01E1 52A8	PROG11_MPPA	Programmable range 11, memory page protection attributes
0x01E1 52AC - 0x01E1 52AF	-	Reserved
0x01E1 52B0	PROG12_MPSAR	Programmable range 12, start address
0x01E1 52B4	PROG12_MPEAR	Programmable range 12, end address
0x01E1 52B8	PROG12_MPPA	Programmable range 12, memory page protection attributes
0x01E1 52BC - 0x01E1 52FF	-	Reserved
0x01E1 5300	FLTADDRR	Fault address
0x01E1 5304	FLTSTAT	Fault status
0x01E1 5308	FLTCLR	Fault clear
0x01E1 530C - 0x01E1 5FFF	-	Reserved

6.13 MMC / SD / SDIO (MMCSD0, MMCSD1)

6.13.1 MMCSD Peripheral Description

The device includes an two MMCSD controllers which are compliant with MMC V4.0, Secure Digital Part 1 Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications.

The MMC/SD Controller have following features:

MultiMediaCard (MMC)
Secure Digital (SD) Memory Card
MMC/SD protocol support
SD high capacity support
SDIO protocol support
Programmable clock frequency
512 bit Read/Write FIFO to lower system overhead
Slave EDMA transfer capability

The device MMC/SD Controller does not support SPI mode.

6.13.2 MMCSD Peripheral Register Description(s)

Table 6-39 Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers

MMCSD0 BYTE ADDRESS	MMCSD1 BYTE ADDRESS	ACRONYM	REGISTER DESCSRIPTION
0x01C4 0000	0x01E1 B000	MMCCTL	MMC Control Register
0x01C4 0004	0x01E1 B004	MMCCLK	MMC Memory Clock Control Register
0x01C4 0008	0x01E1 B008	MMCST0	MMC Status Register 0
0x01C4 000C	0x01E1 B00C	MMCST1	MMC Status Register 1
0x01C4 0010	0x01E1 B010	MMCIM	MMC Interrupt Mask Register
0x01C4 0014	0x01E1 B014	MMCTOR	MMC Response Time-Out Register
0x01C4 0018	0x01E1 B018	MMCTOD	MMC Data Read Time-Out Register
0x01C4 001C	0x01E1 B01C	MMCBLEN	MMC Block Length Register
0x01C4 0020	0x01E1 B020	MMCNBLK	MMC Number of Blocks Register
0x01C4 0024	0x01E1 B024	MMCNBLC	MMC Number of Blocks Counter Register
0x01C4 0028	0x01E1 B028	MMCDRR	MMC Data Receive Register
0x01C4 002C	0x01E1 B02C	MMCDXR	MMC Data Transmit Register
0x01C4 0030	0x01E1 B030	MMCCMD	MMC Command Register
0x01C4 0034	0x01E1 B034	MMCARGHL	MMC Argument Register
0x01C4 0038	0x01E1 B038	MMCRSP01	MMC Response Register 0 and 1
0x01C4 003C	0x01E1 B03C	MMCRSP23	MMC Response Register 2 and 3
0x01C4 0040	0x01E1 B040	MMCRSP45	MMC Response Register 4 and 5
0x01C4 0044	0x01E1 B044	MMCRSP67	MMC Response Register 6 and 7
0x01C4 0048	0x01E1 B048	MMCDRSP	MMC Data Response Register
0x01C4 0050	0x01E1 B050	MMCCIDX	MMC Command Index Register
0x01C4 0064	0x01E1 B064	SDIOCTL	SDIO Control Register
0x01C4 0068	0x01E1 B068	SDIOST0	SDIO Status Register 0
0x01C4 006C	0x01E1 B06C	SDIOIEN	SDIO Interrupt Enable Register
0x01C4 0070	0x01E1 B070	SDIOIST	SDIO Interrupt Status Register
0x01C4 0074	0x01E1 B074	MMCFIFOCTL	MMC FIFO Control Register

6.13.3 MMC/SD Electrical Data/Timing

Table 6-40 through Table 6-41 assume testing over recommended operating conditions.

Table 6-40 Timing Requirements for MMC/SD
(see Figure 6-27 and Figure 6-29)

NO.			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
1	t_{su(CMDV-CLKH)}	Setup time, MMCSD_CMD valid before MMCSD_CLK high	4		4		6		ns
2	t_h(CLKH-CMDV)	Hold time, MMCSD_CMD valid after MMCSD_CLK high	2.5		2.5		2.5		ns
3	t_{su(DATV-CLKH)}	Setup time, MMCSD_DATx valid before MMCSD_CLK high	4.5		5		6		ns
4	t_h(CLKH-DATV)	Hold time, MMCSD_DATx valid after MMCSD_CLK high	2.5		2.5		2.5		ns

Table 6-41 Switching Characteristics for MMC/SD (see Figure 6-26 through Figure 6-29)

NO.	PARAMETER		1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER		MIN	MAX	MIN	MAX	MIN	MAX	UNIT
7	f_(CLK)	Operating frequency, MMCSD_CLK	0	52	0	50	0	25	MHz
8	f_{(CLK_ID)}	Identification mode frequency, MMCSD_CLK	0	400	0	400	0	400	KHz
9	t_W(CLKL)	Pulse width, MMCSD_CLK low	6.5		6.5		10		ns
10	t_W(CLKH)	Pulse width, MMCSD_CLK high	6.5		6.5		10		ns
11	t_r(CLK)	Rise time, MMCSD_CLK		3		3		10	ns
12	t_f(CLK)	Fall time, MMCSD_CLK		3		3		10	ns
13	t_d(CLKL-CMD)	Delay time, MMCSD_CLK low to MMCSD_CMD transition	-4	2.5	-4	3	-4	4	ns
14	t_d(CLKL-DAT)	Delay time, MMCSD_CLK low to MMCSD_DATx transition	-4	3.3	-4	3.5	-4	4	ns

Figure 6-26 MMC/SD Host Command Timing

Figure 6-27 MMC/SD Card Response Timing

Figure 6-28 MMC/SD Host Write Timing

Figure 6-29 MMC/SD Host Read and Card CRC Status Timing

6.14 Multichannel Audio Serial Port (McASP)

The McASP serial port is specifically designed for multichannel audio applications. Its key features are:

Flexible clock and frame sync generation logic and on-chip dividers
Up to sixteen transmit or receive data pins and serializers
Large number of serial data format options, including:
- TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst)
- Time slots of 8,12,16, 20, 24, 28, and 32 bits
- First bit delay 0, 1, or 2 clocks
- MSB or LSB first bit order
- Left- or right-aligned data words within time slots
DIT Mode with 384-bit Channel Status and 384-bit User Data registers
Extensive error checking and mute generation logic
All unused pins GPIO-capable

Transmit & Receive FIFO Buffers allow the McASP to operate at a higher sample rate by making it more tolerant to DMA latency.
Dynamic Adjustment of Clock Dividers
- Clock Divider Value may be changed without resetting the McASP

Figure 6-30 McASP Block Diagram

6.14.1 McASP Peripheral Registers Description(s)

Registers for the McASP are summarized in Table 6-42. The registers are accessed through the peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can also be accessed through the DMA port, as listed in Table 6-43

Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-44. Note that the AFIFO Write FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control registers are accessed through the peripheral configuration port.

Table 6-42 McASP Registers Accessed Through Peripheral Configuration Port

BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01D0 0000	REV	Revision identification register
0x01D0 0010	PFUNC	Pin function register
0x01D0 0014	PDIR	Pin direction register
0x01D0 0018	PDOUT	Pin data output register
0x01D0 001C	PDIN	Read returns: Pin data input register
0x01D0 001C	PDSET	Writes affect: Pin data set register (alternate write address: PDOUT)
0x01D0 0020	PDCLR	Pin data clear register (alternate write address: PDOUT)
0x01D0 0044	GBLCTL	Global control register
0x01D0 0048	AMUTE	Audio mute control register
0x01D0 004C	DLBCTL	Digital loopback control register
0x01D0 0050	DITCTL	DIT mode control register
0x01D0 0060	RGBLCTL	Receiver global control register: Alias of GBLCTL, only receive bits are affected - allows receiver to be reset independently from transmitter
0x01D0 0064	RMASK	Receive format unit bit mask register
0x01D0 0068	RFMT	Receive bit stream format register
0x01D0 006C	AFSRCTL	Receive frame sync control register
0x01D0 0070	ACLKRCTL	Receive clock control register
0x01D0 0074	AHCLKRCTL	Receive high-frequency clock control register
0x01D0 0078	RTDM	Receive TDM time slot 0-31 register
0x01D0 007C	RINTCTL	Receiver interrupt control register
0x01D0 0080	RSTAT	Receiver status register
0x01D0 0084	RSLOT	Current receive TDM time slot register
0x01D0 0088	RCLKCHK	Receive clock check control register
0x01D0 008C	REVTCTL	Receiver DMA event control register
0x01D0 00A0	XGBLCTL	Transmitter global control register. Alias of GBLCTL, only transmit bits are affected - allows transmitter to be reset independently from receiver
0x01D0 00A4	XMASK	Transmit format unit bit mask register
0x01D0 00A8	XFMT	Transmit bit stream format register
0x01D0 00AC	AFSXCTL	Transmit frame sync control register
0x01D0 00B0	ACLKXCTL	Transmit clock control register
0x01D0 00B4	AHCLKXCTL	Transmit high-frequency clock control register
0x01D0 00B8	XTDM	Transmit TDM time slot 0-31 register
0x01D0 00BC	XINTCTL	Transmitter interrupt control register
0x01D0 00C0	XSTAT	Transmitter status register
0x01D0 00C4	XSLOT	Current transmit TDM time slot register
0x01D0 00C8	XCLKCHK	Transmit clock check control register
0x01D0 00CC	XEVTCTL	Transmitter DMA event control register
0x01D0 0100	DITCSRA0	Left (even TDM time slot) channel status register (DIT mode) 0
0x01D0 0104	DITCSRA1	Left (even TDM time slot) channel status register (DIT mode) 1
0x01D0 0108	DITCSRA2	Left (even TDM time slot) channel status register (DIT mode) 2
0x01D0 010C	DITCSRA3	Left (even TDM time slot) channel status register (DIT mode) 3
0x01D0 0110	DITCSRA4	Left (even TDM time slot) channel status register (DIT mode) 4
0x01D0 0114	DITCSRA5	Left (even TDM time slot) channel status register (DIT mode) 5
0x01D0 0118	DITCSRB0	Right (odd TDM time slot) channel status register (DIT mode) 0
0x01D0 011C	DITCSRB1	Right (odd TDM time slot) channel status register (DIT mode) 1
0x01D0 0120	DITCSRB2	Right (odd TDM time slot) channel status register (DIT mode) 2
0x01D0 0124	DITCSRB3	Right (odd TDM time slot) channel status register (DIT mode) 3
0x01D0 0128	DITCSRB4	Right (odd TDM time slot) channel status register (DIT mode) 4
0x01D0 012C	DITCSRB5	Right (odd TDM time slot) channel status register (DIT mode) 5
0x01D0 0130	DITUDRA0	Left (even TDM time slot) channel user data register (DIT mode) 0
0x01D0 0134	DITUDRA1	Left (even TDM time slot) channel user data register (DIT mode) 1
0x01D0 0138	DITUDRA2	Left (even TDM time slot) channel user data register (DIT mode) 2
0x01D0 013C	DITUDRA3	Left (even TDM time slot) channel user data register (DIT mode) 3
0x01D0 0140	DITUDRA4	Left (even TDM time slot) channel user data register (DIT mode) 4
0x01D0 0144	DITUDRA5	Left (even TDM time slot) channel user data register (DIT mode) 5
0x01D0 0148	DITUDRB0	Right (odd TDM time slot) channel user data register (DIT mode) 0
0x01D0 014C	DITUDRB1	Right (odd TDM time slot) channel user data register (DIT mode) 1
0x01D0 0150	DITUDRB2	Right (odd TDM time slot) channel user data register (DIT mode) 2
0x01D0 0154	DITUDRB3	Right (odd TDM time slot) channel user data register (DIT mode) 3
0x01D0 0158	DITUDRB4	Right (odd TDM time slot) channel user data register (DIT mode) 4
0x01D0 015C	DITUDRB5	Right (odd TDM time slot) channel user data register (DIT mode) 5
0x01D0 0180	SRCTL0	Serializer control register 0
0x01D0 0184	SRCTL1	Serializer control register 1
0x01D0 0188	SRCTL2	Serializer control register 2
0x01D0 018C	SRCTL3	Serializer control register 3
0x01D0 0190	SRCTL4	Serializer control register 4
0x01D0 0194	SRCTL5	Serializer control register 5
0x01D0 0198	SRCTL6	Serializer control register 6
0x01D0 019C	SRCTL7	Serializer control register 7
0x01D0 01A0	SRCTL8	Serializer control register 8
0x01D0 01A4	SRCTL9	Serializer control register 9
0x01D0 01A8	SRCTL10	Serializer control register 10
0x01D0 01AC	SRCTL11	Serializer control register 11
0x01D0 01B0	SRCTL12	Serializer control register 12
0x01D0 01B4	SRCTL13	Serializer control register 13
0x01D0 01B8	SRCTL14	Serializer control register 14
0x01D0 01BC	SRCTL15	Serializer control register 15
0x01D0 0200	XBUF0⁽¹⁾	Transmit buffer register for serializer 0
0x01D0 0204	XBUF1⁽¹⁾	Transmit buffer register for serializer 1
0x01D0 0208	XBUF2⁽¹⁾	Transmit buffer register for serializer 2
0x01D0 020C	XBUF3⁽¹⁾	Transmit buffer register for serializer 3
0x01D0 0210	XBUF4⁽¹⁾	Transmit buffer register for serializer 4
0x01D0 0214	XBUF5⁽¹⁾	Transmit buffer register for serializer 5
0x01D0 0218	XBUF6⁽¹⁾	Transmit buffer register for serializer 6
0x01D0 021C	XBUF7⁽¹⁾	Transmit buffer register for serializer 7
0x01D0 0220	XBUF8⁽¹⁾	Transmit buffer register for serializer 8
0x01D0 0224	XBUF9⁽¹⁾	Transmit buffer register for serializer 9
0x01D0 0228	XBUF10⁽¹⁾	Transmit buffer register for serializer 10
0x01D0 022C	XBUF11⁽¹⁾	Transmit buffer register for serializer 11
0x01D0 0230	XBUF12⁽¹⁾	Transmit buffer register for serializer 12
0x01D0 0234	XBUF13⁽¹⁾	Transmit buffer register for serializer 13
0x01D0 0238	XBUF14⁽¹⁾	Transmit buffer register for serializer 14
0x01D0 023C	XBUF15⁽¹⁾	Transmit buffer register for serializer 15
0x01D0 0280	RBUF0⁽²⁾	Receive buffer register for serializer 0
0x01D0 0284	RBUF1⁽²⁾	Receive buffer register for serializer 1
0x01D0 0288	RBUF2⁽²⁾	Receive buffer register for serializer 2
0x01D0 028C	RBUF3⁽²⁾	Receive buffer register for serializer 3
0x01D0 0290	RBUF4⁽²⁾	Receive buffer register for serializer 4
0x01D0 0294	RBUF5⁽²⁾	Receive buffer register for serializer 5
0x01D0 0298	RBUF6⁽²⁾	Receive buffer register for serializer 6
0x01D0 029C	RBUF7⁽²⁾	Receive buffer register for serializer 7
0x01D0 02A0	RBUF8⁽²⁾	Receive buffer register for serializer 8
0x01D0 02A4	RBUF9⁽²⁾	Receive buffer register for serializer 9
0x01D0 02A8	RBUF10⁽²⁾	Receive buffer register for serializer 10
0x01D0 02AC	RBUF11⁽²⁾	Receive buffer register for serializer 11
0x01D0 02B0	RBUF12⁽²⁾	Receive buffer register for serializer 12
0x01D0 02B4	RBUF13⁽²⁾	Receive buffer register for serializer 13
0x01D0 02B8	RBUF14⁽²⁾	Receive buffer register for serializer 14
0x01D0 02BC	RBUF15⁽²⁾	Receive buffer register for serializer 15

(1) Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT.

(2) Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.

Table 6-43 McASP Registers Accessed Through DMA Port

ACCESS TYPE	BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
Read Accesses	0x01D0 2000	RBUF	Receive buffer DMA port address. Cycles through receive serializers, skipping over transmit serializers and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Reads from DMA port only if XBUSEL = 0 in XFMT.
Write Accesses	0x01D0 2000	XBUF	Transmit buffer DMA port address. Cycles through transmit serializers, skipping over receive and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Writes to DMA port only if RBUSEL = 0 in RFMT.

Table 6-44 McASP AFIFO Registers Accessed Through Peripheral Configuration Port

BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01D0 1000	AFIFOREV	AFIFO revision identification register
0x01D0 1010	WFIFOCTL	Write FIFO control register
0x01D0 1014	WFIFOSTS	Write FIFO status register
0x01D0 1018	RFIFOCTL	Read FIFO control register
0x01D0 101C	RFIFOSTS	Read FIFO status register

6.14.2 McASP Electrical Data/Timing

6.14.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing

Table 6-45 and Table 6-47 assume testing over recommended operating conditions (see Figure 6-31 and Figure 6-32).

Table 6-45 Timing Requirements for McASP0 (1.3V, 1.2V, 1.1V)⁽²⁾⁽⁵⁾

NO.				1.3V, 1.2V		1.1V		UNIT
NO.				MIN	MAX	MIN	MAX	UNIT
1	t_c(AHCLKRX)	Cycle time, AHCLKR/X		25		28		ns
2	t_w(AHCLKRX)	Pulse duration, AHCLKR/X high or low		12.5		14		ns
3	t_c(ACLKRX)	Cycle time, ACLKR/X	AHCLKR/X ext	25⁽¹⁾		28⁽¹⁾		ns
4	t_w(ACLKRX)	Pulse duration, ACLKR/W high or low	AHCLKR/X ext	12.5		14		ns
5	t_{su(AFSRX-ACLKRX)}	Setup time, AFSR/X input to ACLKR/X⁽³⁾	AHCLKR/X int	11.5		12		ns
			AHCLKR/X ext input	4		5		ns
			AHCLKR/X ext output	4		5		ns
6	t_{h(ACLKRX-AFSRX)}	Hold time, AFSR/X input after ACLKR/X⁽³⁾	AHCLKR/X int	-1		-2		ns
			AHCLKR/X ext input	1		1		ns
			AHCLKR/X ext output	1		1		ns
7	t_{su(AXR-ACLKRX)}	Setup time, AXR0[n] input to ACLKR/X⁽³⁾⁽⁴⁾	AHCLKR/X int	11.5		12		ns
7	t_{su(AXR-ACLKRX)}	Setup time, AXR0[n] input to ACLKR/X⁽³⁾⁽⁴⁾	AHCLKR/X ext	4		5		ns
8	t_{h(ACLKRX-AXR)}	Hold time, AXR0[n] input after ACLKR/X⁽³⁾⁽⁴⁾	AHCLKR/X int	-1		-2		ns
			AHCLKR/X ext input	3		4		ns
			AHCLKR/X ext output	3		4		ns

(1) This timing is limited by the timing shown or 2P, whichever is greater.

(2) ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1

(3) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0

(4) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0

(5) P = SYSCLK2 period

Table 6-46 Timing Requirements for McASP0 (1.0V)⁽²⁾⁽⁵⁾

NO.				1.0V		UNIT
NO.				MIN	MAX	UNIT
1	t_c(AHCLKRX)	Cycle time, AHCLKR/X		35		ns
2	t_w(AHCLKRX)	Pulse duration, AHCLKR/X high or low		17.5		ns
3	t_c(ACLKRX)	Cycle time, ACLKR/X	AHCLKR/X ext	35⁽¹⁾		ns
4	t_w(ACLKRX)	Pulse duration, ACLKR/W high or low	AHCLKR/X ext	17.5		ns
5	t_{su(AFSRX-ACLKRX)}	Setup time, AFSR/X input to ACLKR/X⁽³⁾	AHCLKR/X int	16		ns
			AHCLKR/X ext input	5.5		ns
			AHCLKR/X ext output	5.5		ns
6	t_{h(ACLKRX-AFSRX)}	Hold time, AFSR/X input after ACLKR/X⁽³⁾	AHCLKR/X int	-2		ns
			AHCLKR/X ext input	1		ns
			AHCLKR/X ext output	1		ns
7	t_{su(AXR-ACLKRX)}	Setup time, AXR0[n] input to ACLKR/X⁽³⁾⁽⁴⁾	AHCLKR/X int	16		ns
7	t_{su(AXR-ACLKRX)}	Setup time, AXR0[n] input to ACLKR/X⁽³⁾⁽⁴⁾	AHCLKR/X ext	5.5		ns
8	t_{h(ACLKRX-AXR)}	Hold time, AXR0[n] input after ACLKR/X⁽³⁾⁽⁴⁾	AHCLKR/X int	-2		ns
			AHCLKR/X ext input	5		ns
			AHCLKR/X ext output	5		ns

(1) This timing is limited by the timing shown or 2P, whichever is greater.

(3) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0

(4) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0

(5) P = SYSCLK2 period

Table 6-47 Switching Characteristics for McASP0 (1.3V, 1.2V, 1.1V)⁽¹⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	UNIT
9	t_c(AHCLKRX)	Cycle time, AHCLKR/X		25		28		ns
10	t_w(AHCLKRX)	Pulse duration, AHCLKR/X high or low		AH – 2.5⁽²⁾		AH – 2.5⁽²⁾		ns
11	t_c(ACLKRX)	Cycle time, ACLKR/X	ACLKR/X int	25⁽⁴⁾⁽⁵⁾		28⁽⁴⁾⁽⁵⁾		ns
12	t_w(ACLKRX)	Pulse duration, ACLKR/X high or low	ACLKR/X int	A – 2.5⁽³⁾		A – 2.5⁽³⁾		ns
13	t_{d(ACLKRX-AFSRX)}	Delay time, ACLKR/X transmit edge to AFSX/R output valid⁽⁶⁾	ACLKR/X int	-1	6	-1	8	ns
			ACLKR/X ext input	2	13.5	2	14.5	ns
			ACLKR/X ext output	2	13.5	2	14.5	ns
14	t_{d(ACLKX-AXRV)}	Delay time, ACLKX transmit edge to AXR output valid	ACLKR/X int	-1	6	-1	8	ns
			ACLKR/X ext input	2	13.5	2	15	ns
			ACLKR/X ext output	2	13.5	2	15	ns
15	t_{dis(ACLKX-AXRHZ)}	Disable time, ACLKR/X transmit edge to AXR high impedance following last data bit	ACLKR/X int	0	6	0	8	ns
15	t_{dis(ACLKX-AXRHZ)}		ACLKR/X ext	2	13.5	2	15	ns

(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1

(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.

(3) A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.

(4) P = SYSCLK2 period

(5) This timing is limited by the timing shown or 2P, whichever is greater.

(6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0

Table 6-48 Switching Characteristics for McASP0 (1.0V)⁽¹⁾

NO.	PARAMETER			1.0V		UNIT
NO.	PARAMETER			MIN	MAX	UNIT
9	t_c(AHCLKRX)	Cycle time, AHCLKR/X		35		ns
10	t_w(AHCLKRX)	Pulse duration, AHCLKR/X high or low		AH – 2.5⁽²⁾		ns
11	t_c(ACLKRX)	Cycle time, ACLKR/X	ACLKR/X int	35⁽⁴⁾⁽⁵⁾		ns
12	t_w(ACLKRX)	Pulse duration, ACLKR/X high or low	ACLKR/X int	A – 2.5⁽³⁾		ns
13	t_{d(ACLKRX-AFSRX)}	Delay time, ACLKR/X transmit edge to AFSX/R output valid⁽⁶⁾	ACLKR/X int	-0.5	10	ns
			ACLKR/X ext input	2	19	ns
			ACLKR/X ext output	2	19	ns
14	t_{d(ACLKX-AXRV)}	Delay time, ACLKX transmit edge to AXR output valid	ACLKR/X int	-0.5	10	ns
			ACLKR/X ext input	2	19	ns
			ACLKR/X ext output	2	19	ns
15	t_{dis(ACLKX-AXRHZ)}	Disable time, ACLKR/X transmit edge to AXR high impedance following last data bit	ACLKR/X int	0	10	ns
15	t_{dis(ACLKX-AXRHZ)}		ACLKR/X ext	2	19	ns

(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.

(3) A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.

(4) P = SYSCLK2 period

(5) This timing is limited by the timing shown or 2P, whichever is greater.

(6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0

A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in).

B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in).

Figure 6-31 McASP Input Timings

A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in).

B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in).

Figure 6-32 McASP Output Timings

6.15 Multichannel Buffered Serial Port (McBSP)

The McBSP provides these functions:

Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
External shift clock or an internal, programmable frequency shift clock for data transfer
Transmit & Receive FIFO Buffers allow the McBSP to operate at a higher sample rate by making it more tolerant to DMA latency

If internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater.

6.15.1 McBSP Peripheral Register Description(s)

Table 6-49 McBSP/FIFO Registers

McBSP0 BYTE ADDRESS	McBSP1 BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
McBSP Registers
0x01D1 0000	0x01D1 1000	DRR	McBSP Data Receive Register (read-only)
0x01D1 0004	0x01D1 1004	DXR	McBSP Data Transmit Register
0x01D1 0008	0x01D1 1008	SPCR	McBSP Serial Port Control Register
0x01D1 000C	0x01D1 100C	RCR	McBSP Receive Control Register
0x01D1 0010	0x01D1 1010	XCR	McBSP Transmit Control Register
0x01D1 0014	0x01D1 1014	SRGR	McBSP Sample Rate Generator register
0x01D1 0018	0x01D1 1018	MCR	McBSP Multichannel Control Register
0x01D1 001C	0x01D1 101C	RCERE0	McBSP Enhanced Receive Channel Enable Register 0 Partition A/B
0x01D1 0020	0x01D1 1020	XCERE0	McBSP Enhanced Transmit Channel Enable Register 0 Partition A/B
0x01D1 0024	0x01D1 1024	PCR	McBSP Pin Control Register
0x01D1 0028	0x01D1 1028	RCERE1	McBSP Enhanced Receive Channel Enable Register 1 Partition C/D
0x01D1 002C	0x01D1 102C	XCERE1	McBSP Enhanced Transmit Channel Enable Register 1 Partition C/D
0x01D1 0030	0x01D1 1030	RCERE2	McBSP Enhanced Receive Channel Enable Register 2 Partition E/F
0x01D1 0034	0x01D1 1034	XCERE2	McBSP Enhanced Transmit Channel Enable Register 2 Partition E/F
0x01D1 0038	0x01D1 1038	RCERE3	McBSP Enhanced Receive Channel Enable Register 3 Partition G/H
0x01D1 003C	0x01D1 103C	XCERE3	McBSP Enhanced Transmit Channel Enable Register 3 Partition G/H
McBSP FIFO Control and Status Registers
0x01D1 0800	0x01D1 1800	BFIFOREV	BFIFO Revision Identification Register
0x01D1 0810	0x01D1 1810	WFIFOCTL	Write FIFO Control Register
0x01D1 0814	0x01D1 1814	WFIFOSTS	Write FIFO Status Register
0x01D1 0818	0x01D1 1818	RFIFOCTL	Read FIFO Control Register
0x01D1 081C	0x01D1 181C	RFIFOSTS	Read FIFO Status Register
McBSP FIFO Data Registers
0x01F1 0000	0x01F1 1000	RBUF	McBSP FIFO Receive Buffer
0x01F1 0000	0x01F1 1000	XBUF	McBSP FIFO Transmit Buffer

6.15.2 McBSP Electrical Data/Timing

The following assume testing over recommended operating conditions.

6.15.2.1 Multichannel Buffered Serial Port (McBSP) Timing

Table 6-50 Timing Requirements for McBSP0 [1.3V, 1.2V, 1.1V]⁽¹⁾ (see Figure 6-33)

NO.				1.3V, 1.2V		1.1V		UNIT
NO.				MIN	MAX	MIN	MAX	UNIT
2	t_c(CKRX)	Cycle time, CLKR/X	CLKR/X ext	2P or 20⁽²⁾⁽³⁾		2P or 25⁽²⁾⁽³⁾		ns
3	t_w(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X ext	P - 1⁽⁴⁾		P - 1⁽⁴⁾		ns
5	t_su(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR int	14		15.5		ns
5	t_su(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR ext	4		5		ns
6	t_h(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR int	6		6		ns
6	t_h(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR ext	3		3		ns
7	t_su(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR int	14		15.5		ns
7	t_su(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR ext	4		5		ns
8	t_h(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR int	3		3		ns
8	t_h(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR ext	3		3		ns
10	t_su(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKX int	14		15.5		ns
10	t_su(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKX ext	4		5		ns
11	t_h(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKX int	6		6		ns
11	t_h(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKX ext	3		3		ns

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.

(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.

(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

Table 6-51 Timing Requirements for McBSP0 [1.0V]⁽¹⁾ (see Figure 6-33)

NO.				1.0V		UNIT
NO.				MIN	MAX	UNIT
2	t_c(CKRX)	Cycle time, CLKR/X	CLKR/X ext	2P or 26.6⁽²⁾⁽³⁾		ns
3	t_w(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X ext	P - 1⁽⁴⁾		ns
5	t_su(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR int	20		ns
5	t_su(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR ext	5		ns
6	t_h(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR int	6		ns
6	t_h(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR ext	3		ns
7	t_su(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR int	20		ns
7	t_su(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR ext	5		ns
8	t_h(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR int	3		ns
8	t_h(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR ext	3		ns
10	t_su(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKX int	20		ns
10	t_su(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKX ext	5		ns
11	t_h(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKX int	6		ns
11	t_h(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKX ext	3		ns

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.

(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

Table 6-52 Switching Characteristics for McBSP0 [1.3V, 1.2V, 1.1V]⁽¹⁾⁽²⁾
(see Figure 6-33)

NO.	PARAMETER			1.3V, 1.2V		1.1V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	UNIT
1	t_{d(CKSH-CKRXH)}	Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input		2	14.5	2	16	ns
2	t_c(CKRX)	Cycle time, CLKR/X	CLKR/X int	2P or 20⁽³⁾⁽⁴⁾⁽⁵⁾		2P or 25⁽³⁾⁽⁴⁾⁽⁵⁾		ns
3	t_w(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X int	C - 2⁽⁶⁾	C + 2⁽⁶⁾	C - 2⁽⁶⁾	C + 2⁽⁶⁾	ns
4	t_d(CKRH-FRV)	Delay time, CLKR high to internal FSR valid	CLKR int	-4	5.5	-4	5.5	ns
4	t_d(CKRH-FRV)	Delay time, CLKR high to internal FSR valid	CLKR ext	2	14.5	2	16	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX int	-4	5.5	-4	5.5	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX ext	2	14.5	2	16	ns
12	t_{dis(CKXH-DXHZ)}	Disable time, DX high impedance following last data bit from CLKX high	CLKX int	-4	7.5	-5.5	7.5	ns
12	t_{dis(CKXH-DXHZ)}		CLKX ext	-2	16	-22	16	ns
13	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	CLKX int	-4 + D1⁽⁷⁾	5.5 + D2⁽⁷⁾	-4 + D1⁽⁷⁾	5.5 + D2⁽⁷⁾	ns
13	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	CLKX ext	2 + D1⁽⁷⁾	14.5 + D2⁽⁷⁾	2 + D1⁽⁷⁾	16 + D2⁽⁷⁾	ns
14	t_d(FXH-DXV)	Delay time, FSX high to DX valid	FSX int	-4⁽⁸⁾	5⁽⁸⁾	-4⁽⁸⁾	5⁽⁸⁾	ns
14	t_d(FXH-DXV)	ONLY applies when in data delay 0 (XDATDLY = 00b) mode	FSX ext	-2⁽⁸⁾	14.5⁽⁸⁾	-2⁽⁸⁾	16⁽⁸⁾	ns

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2) Minimum delay times also represent minimum output hold times.

(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.

(4) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.

(5) Use whichever value is greater.

(6) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).

(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P

(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P

Table 6-53 Switching Characteristics for McBSP0 [1.0V]⁽¹⁾ ⁽²⁾
(see Figure 6-33)

NO.	PARAMETER			1.0V		UNIT
NO.	PARAMETER			MIN	MAX	UNIT
1	t_{d(CKSH-CKRXH)}	Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input		3	21.5	ns
2	t_c(CKRX)	Cycle time, CLKR/X	CLKR/X int	2P or 26.6⁽³⁾⁽³⁾⁽⁴⁾		ns
3	t_w(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X int	C - 2⁽⁵⁾	C + 2⁽⁵⁾	ns
4	t_d(CKRH-FRV)	Delay time, CLKR high to internal FSR valid	CLKR int	-4	10	ns
4	t_d(CKRH-FRV)	Delay time, CLKR high to internal FSR valid	CLKR ext	2.5	21.5	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX int	-4	10	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX ext	2.5	21.5	ns
12	t_{dis(CKXH-DXHZ)}	Disable time, DX high impedance following last data bit from CLKX high	CLKX int	-4	10	ns
12	t_{dis(CKXH-DXHZ)}		CLKX ext	-2	21.5	ns
13	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	CLKX int	-4 + D1⁽⁶⁾	10 + D2⁽⁶⁾	ns
13	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	CLKX ext	2.5 + D1⁽⁶⁾	21.5 + D2⁽⁶⁾	ns
14	t_d(FXH-DXV)	Delay time, FSX high to DX valid	FSX int	-4⁽⁷⁾	5⁽⁷⁾	ns
14	t_d(FXH-DXV)	ONLY applies when in data delay 0 (XDATDLY = 00b) mode	FSX ext	-2⁽⁷⁾	21.5⁽⁷⁾	ns

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2) Minimum delay times also represent minimum output hold times.

(3) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.

(4) Use whichever value is greater.

(5) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).

(6) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P

(7) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P

Table 6-54 Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V]⁽¹⁾ (see Figure 6-33)

NO.				1.3V, 1.2V		1.1V		UNIT
NO.				MIN	MAX	MIN	MAX	UNIT
2	t_c(CKRX)	Cycle time, CLKR/X	CLKR/X ext	2P or 20⁽²⁾⁽³⁾		2P or 25⁽²⁾ ⁽³⁾		ns
3	t_w(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X ext	P - 1⁽⁴⁾		P - 1⁽⁴⁾		ns
5	t_su(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR int	15		18		ns
5	t_su(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR ext	5		5		ns
6	t_h(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR int	6		6		ns
6	t_h(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR ext	3		3		ns
7	t_su(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR int	15		18		ns
7	t_su(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR ext	5		5		ns
8	t_h(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR int	3		3		ns
8	t_h(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR ext	3		3		ns
10	t_su(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKX int	15		18		ns
10	t_su(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKX ext	5		5		ns
11	t_h(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKX int	6		6		ns
11	t_h(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKX ext	3		3		ns

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.

(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

Table 6-55 Timing Requirements for McBSP1 [1.0V]⁽¹⁾ (see Figure 6-33)

NO.				1.0V		UNIT
NO.				MIN	MAX	UNIT
2	t_c(CKRX)	Cycle time, CLKR/X	CLKR/X ext	2P or 26.6⁽²⁾⁽³⁾		ns
3	t_w(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X ext	P - 1⁽⁴⁾		ns
5	t_su(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR int	21		ns
5	t_su(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR ext	10		ns
6	t_h(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR int	6		ns
6	t_h(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR ext	3		ns
7	t_su(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR int	21		ns
7	t_su(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR ext	10		ns
8	t_h(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR int	3		ns
8	t_h(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR ext	3		ns
10	t_su(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKX int	21		ns
10	t_su(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKX ext	10		ns
11	t_h(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKX int	6		ns
11	t_h(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKX ext	3		ns

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.

(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

Table 6-56 Switching Characteristics for McBSP1 [1.3V, 1.2V, 1.1V]⁽¹⁾ ⁽²⁾
(see Figure 6-33)

NO.	PARAMETER			1.3V, 1.2V		1.1V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	UNIT
1	t_{d(CKSH-CKRXH)}	Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input		0.5	16.5	1.5	18	ns
2	t_c(CKRX)	Cycle time, CLKR/X	CLKR/X int	2P or 20⁽³⁾⁽³⁾⁽⁴⁾		2P or 25⁽³⁾⁽³⁾ ⁽⁴⁾		ns
3	t_w(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X int	C - 2⁽⁵⁾	C + 2⁽⁵⁾	C - 2⁽⁵⁾	C + 2⁽⁵⁾	ns
4	t_d(CKRH-FRV)	Delay time, CLKR high to internal FSR valid	CLKR int	-4	6.5	-4	13	ns
4	t_d(CKRH-FRV)	Delay time, CLKR high to internal FSR valid	CLKR ext	1	16.5	1	18	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX int	-4	6.5	-4	13	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX ext	1	16.5	1	18	ns
12	t_{dis(CKXH-DXHZ)}	Disable time, DX high impedance following last data bit from CLKX high	CLKX int	-4	6.5	-4	13	ns
12	t_{dis(CKXH-DXHZ)}		CLKX ext	-2	16.5	-2	18	ns
13	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	CLKX int	-4 + D1⁽⁶⁾	6.5 + D2⁽⁶⁾	-4 + D1⁽⁶⁾	13 + D2⁽⁶⁾	ns
13	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	CLKX ext	1 + D1⁽⁶⁾	16.5 + D2⁽⁶⁾	1 + D1⁽⁶⁾	18 + D2⁽⁶⁾	ns
14	t_d(FXH-DXV)	Delay time, FSX high to DX valid	FSX int	-4⁽⁷⁾	6.5⁽⁷⁾	-4⁽⁷⁾	13⁽⁷⁾	ns
14	t_d(FXH-DXV)	ONLY applies when in data delay 0 (XDATDLY = 00b) mode	FSX ext	-2⁽⁷⁾	16.5⁽⁷⁾	-2⁽⁷⁾	18⁽⁸⁾	ns

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2) Minimum delay times also represent minimum output hold times.

(3) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.

(4) Use whichever value is greater.

(7) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P

Table 6-57 Switching Characteristics for McBSP1 [1.0V]⁽¹⁾ ⁽²⁾
(see Figure 6-33)

NO.	PARAMETER			1.0V		UNIT
NO.	PARAMETER			MIN	MAX	UNIT
1	t_{d(CKSH-CKRXH)}	Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input		1.5	23	ns
2	t_c(CKRX)	Cycle time, CLKR/X	CLKR/X int	2P or 26.6⁽³⁾⁽⁴⁾⁽⁵⁾		ns
3	t_w(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X int	C - 2⁽⁶⁾	C + 2⁽⁶⁾	ns
4	t_d(CKRH-FRV)	Delay time, CLKR high to internal FSR valid	CLKR int	-4	13	ns
4	t_d(CKRH-FRV)	Delay time, CLKR high to internal FSR valid	CLKR ext	2.5	23	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX int	-4	13	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX ext	1	23	ns
12	t_{dis(CKXH-DXHZ)}	Disable time, DX high impedance following last data bit from CLKX high	CLKX int	-4	13	ns
12	t_{dis(CKXH-DXHZ)}		CLKX ext	-2	23	ns
13	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	CLKX int	-4 + D1⁽⁶⁾	13 + D2⁽⁷⁾	ns
13	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	CLKX ext	1 + D1⁽⁷⁾	23 + D2⁽⁷⁾	ns
14	t_d(FXH-DXV)	Delay time, FSX high to DX valid	FSX int	-4⁽⁸⁾	13⁽⁸⁾	ns
14	t_d(FXH-DXV)	ONLY applies when in data delay 0 (XDATDLY = 00b) mode	FSX ext	-2⁽⁸⁾	23⁽⁸⁾	ns

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2) Minimum delay times also represent minimum output hold times.

(4) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.

(5) Use whichever value is greater.

(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P

A. No. 13 applies to the first data bit only when XDATDLY ≠ 0.

Figure 6-33 McBSP Timing

Table 6-58 Timing Requirements for McBSP0 FSR When GSYNC = 1 (see Figure 6-34)

NO.			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
1	t_su(FRH-CKSH)	Setup time, FSR high before CLKS high	4		4.5		5		ns
2	t_h(CKSH-FRH)	Hold time, FSR high after CLKS high	4		4		4		ns

Table 6-59 Timing Requirements for McBSP1 FSR When GSYNC = 1 (see Figure 6-34)

NO.			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
1	t_su(FRH-CKSH)	Setup time, FSR high before CLKS high	5		5		10		ns
2	t_h(CKSH-FRH)	Hold time, FSR high after CLKS high	4		4		4		ns

Figure 6-34 FSR Timing When GSYNC = 1

6.16 Serial Peripheral Interface Ports (SPI0, SPI1)

Figure 6-35 is a block diagram of the SPI module, which is a simple shift register and buffer plus control logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many data formatting options.

Figure 6-35 Block Diagram of SPI Module

The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and SPIx_SOMI) and two optional pins (SPIx_SCS, SPIx_ENA).

The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are other slave devices on the same SPI port. The device will only shift data and drive the SPIx_SOMI pin when SPIx_SCS is held low.

In slave mode, SPIx_ENA is an optional output. The SPIx_ENA output provides the status of the internal transmit buffer (SPIDAT0/1 registers). In four-pin mode with the enable option, SPIx_ENA is asserted only when the transmit buffer is full, indicating that the slave is ready to begin another transfer. In five-pin mode, the SPIx_ENA is additionally qualified by SPIx_SCS being asserted. This allows a single handshake line to be shared by multiple slaves on the same SPI bus.

In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI communications and, on average, increases SPI bus throughput since the master does not need to delay each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer can begin as soon as both the master and slave have actually serviced the previous SPI transfer.

Figure 6-36 Illustration of SPI Master-to-SPI Slave Connection

6.16.1 SPI Peripheral Registers Description(s)

Table 6-60 is a list of the SPI registers.

Table 6-60 SPIx Configuration Registers

SPI0 BYTE ADDRESS	SPI1 BYTE ADDRESS	ACRONYM	DESCRIPTION
0x01C4 1000	0x01F0 E000	SPIGCR0	Global Control Register 0
0x01C4 1004	0x01F0 E004	SPIGCR1	Global Control Register 1
0x01C4 1008	0x01F0 E008	SPIINT0	Interrupt Register
0x01C4 100C	0x01F0 E00C	SPILVL	Interrupt Level Register
0x01C4 1010	0x01F0 E010	SPIFLG	Flag Register
0x01C4 1014	0x01F0 E014	SPIPC0	Pin Control Register 0 (Pin Function)
0x01C4 1018	0x01F0 E018	SPIPC1	Pin Control Register 1 (Pin Direction)
0x01C4 101C	0x01F0 E01C	SPIPC2	Pin Control Register 2 (Pin Data In)
0x01C4 1020	0x01F0 E020	SPIPC3	Pin Control Register 3 (Pin Data Out)
0x01C4 1024	0x01F0 E024	SPIPC4	Pin Control Register 4 (Pin Data Set)
0x01C4 1028	0x01F0 E028	SPIPC5	Pin Control Register 5 (Pin Data Clear)
0x01C4 102C	0x01F0 E02C	Reserved	Reserved - Do not write to this register
0x01C4 1030	0x01F0 E030	Reserved	Reserved - Do not write to this register
0x01C4 1034	0x01F0 E034	Reserved	Reserved - Do not write to this register
0x01C4 1038	0x01F0 E038	SPIDAT0	Shift Register 0 (without format select)
0x01C4 103C	0x01F0 E03C	SPIDAT1	Shift Register 1 (with format select)
0x01C4 1040	0x01F0 E040	SPIBUF	Buffer Register
0x01C4 1044	0x01F0 E044	SPIEMU	Emulation Register
0x01C4 1048	0x01F0 E048	SPIDELAY	Delay Register
0x01C4 104C	0x01F0 E04C	SPIDEF	Default Chip Select Register
0x01C4 1050	0x01F0 E050	SPIFMT0	Format Register 0
0x01C4 1054	0x01F0 E054	SPIFMT1	Format Register 1
0x01C4 1058	0x01F0 E058	SPIFMT2	Format Register 2
0x01C4 105C	0x01F0 E05C	SPIFMT3	Format Register 3
0x01C4 1060	0x01F0 E060	INTVEC0	Interrupt Vector for SPI INT0
0x01C4 1064	0x01F0 E064	INTVEC1	Interrupt Vector for SPI INT1

6.16.2 SPI Electrical Data/Timing

6.16.2.1 Serial Peripheral Interface (SPI) Timing

Table 6-61 through Table 6-76 assume testing over recommended operating conditions (see Figure 6-37 through Figure 6-40).

Table 6-61 General Timing Requirements for SPI0 Master Modes⁽¹⁾

NO.				1.3V, 1.2V		1.1V		1.0V		UNIT
NO.				MIN	MAX	MIN	MAX	MIN	MAX	UNIT
1	t_c(SPC)M	Cycle Time, SPI0_CLK, All Master Modes		20⁽²⁾	256P	30⁽²⁾	256P	40⁽²⁾	256P	ns
2	t_w(SPCH)M	Pulse Width High, SPI0_CLK, All Master Modes		0.5M-1		0.5M-1		0.5M-1		ns
3	t_w(SPCL)M	Pulse Width Low, SPI0_CLK, All Master Modes		0.5M-1		0.5M-1		0.5M-1		ns
4	t_{d(SIMO_SPC)M}	Delay, initial data bit valid on SPI0_SIMO after initial edge on SPI0_CLK⁽³⁾	Polarity = 0, Phase = 0, to SPI0_CLK rising		5		5		6	ns
			Polarity = 0, Phase = 1, to SPI0_CLK rising		-0.5M+5		-0.5M+5		-0.5M+6
			Polarity = 1, Phase = 0, to SPI0_CLK falling		5		5		6
			Polarity = 1, Phase = 1, to SPI0_CLK falling		-0.5M+5		-0.5M+5		-0.5M+6
5	t_{d(SPC_SIMO)M}	Delay, subsequent bits valid on SPI0_SIMO after transmit edge of SPI0_CLK	Polarity = 0, Phase = 0, from SPI0_CLK rising		5		5		6	ns
			Polarity = 0, Phase = 1, from SPI0_CLK falling		5		5		6
			Polarity = 1, Phase = 0, from SPI0_CLK falling		5		5		6
			Polarity = 1, Phase = 1, from SPI0_CLK rising		5		5		6
6	t_{oh(SPC_SIMO)M}	Output hold time, SPI0_SIMO valid after receive edge of SPI0_CLK	Polarity = 0, Phase = 0, from SPI0_CLK falling	0.5M-3		0.5M-3		0.5M-3		ns
			Polarity = 0, Phase = 1, from SPI0_CLK rising	0.5M-3		0.5M-3		0.5M-3
			Polarity = 1, Phase = 0, from SPI0_CLK rising	0.5M-3		0.5M-3		0.5M-3
			Polarity = 1, Phase = 1, from SPI0_CLK falling	0.5M-3		0.5M-3		0.5M-3
7	t_{su(SOMI_SPC)M}	Input Setup Time, SPI0_SOMI valid before receive edge of SPI0_CLK	Polarity = 0, Phase = 0, to SPI0_CLK falling	1.5		1.5		1.5		ns
			Polarity = 0, Phase = 1, to SPI0_CLK rising	1.5		1.5		1.5
			Polarity = 1, Phase = 0, to SPI0_CLK rising	1.5		1.5		1.5
			Polarity = 1, Phase = 1, to SPI0_CLK falling	1.5		1.5		1.5
8	t_{ih(SPC_SOMI)M}	Input Hold Time, SPI0_SOMI valid after receive edge of SPI0_CLK	Polarity = 0, Phase = 0, from SPI0_CLK falling	4		4		5		ns
			Polarity = 0, Phase = 1, from SPI0_CLK rising	4		4		5
			Polarity = 1, Phase = 0, from SPI0_CLK rising	4		4		5
			Polarity = 1, Phase = 1, from SPI0_CLK falling	4		4		5

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) This timing is limited by the timing shown or 3P, whichever is greater.

(3) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.

Table 6-62 General Timing Requirements for SPI0 Slave Modes⁽¹⁾

NO.				1.3V, 1.2V		1.1V		1.0V		UNIT
NO.				MIN	MAX	MIN	MAX	MIN	MAX	UNIT
9	t_c(SPC)S	Cycle Time, SPI0_CLK, All Slave Modes		40⁽²⁾		50⁽²⁾		60⁽²⁾		ns
10	t_w(SPCH)S	Pulse Width High, SPI0_CLK, All Slave Modes		18		22		27		ns
11	t_w(SPCL)S	Pulse Width Low, SPI0_CLK, All Slave Modes		18		22		27		ns
12	t_{su(SOMI_SPC)S}	Setup time, transmit data written to SPI before initial clock edge from master.⁽³⁾ ⁽⁴⁾	Polarity = 0, Phase = 0, to SPI0_CLK rising	2P		2P		2P		ns
			Polarity = 0, Phase = 1, to SPI0_CLK rising	2P		2P		2P
			Polarity = 1, Phase = 0, to SPI0_CLK falling	2P		2P		2P
			Polarity = 1, Phase = 1, to SPI0_CLK falling	2P		2P		2P
13	t_{d(SPC_SOMI)S}	Delay, subsequent bits valid on SPI0_SOMI after transmit edge of SPI0_CLK	Polarity = 0, Phase = 0, from SPI0_CLK rising		17		20		27	ns
			Polarity = 0, Phase = 1, from SPI0_CLK falling		17		20		27
			Polarity = 1, Phase = 0, from SPI0_CLK falling		17		20		27
			Polarity = 1, Phase = 1, from SPI0_CLK rising		17		20		27
14	t_{oh(SPC_SOMI)S}	Output hold time, SPI0_SOMI valid after receive edge of SPI0_CLK	Polarity = 0, Phase = 0, from SPI0_CLK falling	0.5S-6		0.5S-16		0.5S-20		ns
			Polarity = 0, Phase = 1, from SPI0_CLK rising	0.5S-6		0.5S-16		0.5S-20
			Polarity = 1, Phase = 0, from SPI0_CLK rising	0.5S-6		0.5S-16		0.5S-20
			Polarity = 1, Phase = 1, from SPI0_CLK falling	0.5S-6		0.5S-16		0.5S-20
15	t_{su(SIMO_SPC)S}	Input Setup Time, SPI0_SIMO valid before receive edge of SPI0_CLK	Polarity = 0, Phase = 0, to SPI0_CLK falling	1.5		1.5		1.5		ns
			Polarity = 0, Phase = 1, to SPI0_CLK rising	1.5		1.5		1.5
			Polarity = 1, Phase = 0, to SPI0_CLK rising	1.5		1.5		1.5
			Polarity = 1, Phase = 1, to SPI0_CLK falling	1.5		1.5		1.5
16	t_{ih(SPC_SIMO)S}	Input Hold Time, SPI0_SIMO valid after receive edge of SPI0_CLK	Polarity = 0, Phase = 0, from SPI0_CLK falling	4		4		5		ns
			Polarity = 0, Phase = 1, from SPI0_CLK rising	4		4		5
			Polarity = 1, Phase = 0, from SPI0_CLK rising	4		4		5
			Polarity = 1, Phase = 1, from SPI0_CLK falling	4		4		5

(1) P = SYSCLK2 period; S = t_c(SPC)S(SPI slave bit clock period)

(2) This timing is limited by the timing shown or 3P, whichever is greater.

(3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.

(4) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus cycles must be accounted for to allow data to be written to the SPI module by the CPU.

Table 6-63 Additional SPI0 Master Timings, 4-Pin Enable Option ⁽⁵⁾⁽¹⁾⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
17	t_{d(ENA_SPC)M}	Delay from slave assertion of SPI0_ENA active to first SPI0_CLK from master.⁽³⁾	Polarity = 0, Phase = 0, to SPI0_CLK rising		3P+5		3P+5		3P+6	ns
			Polarity = 0, Phase = 1, to SPI0_CLK rising		0.5M+3P+5		0.5M+3P+5		0.5M+3P+6
			Polarity = 1, Phase = 0, to SPI0_CLK falling		3P+5		3P+5		3P+6
			Polarity = 1, Phase = 1, to SPI0_CLK falling		0.5M+3P+5		0.5M+3P+5		0.5M+3P+6
18	t_{d(SPC_ENA)M}	Max delay for slave to deassert SPI0_ENA after final SPI0_CLK edge to ensure master does not begin the next transfer.⁽⁴⁾	Polarity = 0, Phase = 0, from SPI0_CLK falling		0.5M+P+5		0.5M+P+5		0.5M+P+6	ns
			Polarity = 0, Phase = 1, from SPI0_CLK falling		P+5		P+5		P+6
			Polarity = 1, Phase = 0, from SPI0_CLK rising		0.5M+P+5		0.5M+P+5		0.5M+P+6
			Polarity = 1, Phase = 1, from SPI0_CLK rising		P+5		P+5		P+6

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(3) In the case where the master SPI is ready with new data before SPI0_ENA assertion.

(4) In the case where the master SPI is ready with new data before SPI0_EN A deassertion.

(5) These parameters are in addition to the general timings for SPI master modes (Table 6-61).

Table 6-64 Additional SPI0 Master Timings, 4-Pin Chip Select Option ⁽⁷⁾⁽¹⁾⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
19	t_{d(SCS_SPC)M}	Delay from SPI0_SCS active to first SPI0_CLK⁽³⁾ ⁽⁴⁾	Polarity = 0, Phase = 0, to SPI0_CLK rising	2P-1		2P-2		2P-3		ns
			Polarity = 0, Phase = 1, to SPI0_CLK rising	0.5M+2P-1		0.5M+2P-2		0.5M+2P-3
			Polarity = 1, Phase = 0, to SPI0_CLK falling	2P-1		2P-2		2P-3
			Polarity = 1, Phase = 1, to SPI0_CLK falling	0.5M+2P-1		0.5M+2P-2		0.5M+2P-3
20	t_{d(SPC_SCS)M}	Delay from final SPI0_CLK edge to master deasserting SPI0_SCS ⁽⁵⁾ ⁽⁶⁾	Polarity = 0, Phase = 0, from SPI0_CLK falling	0.5M+P-1		0.5M+P-2		0.5M+P-3		ns
			Polarity = 0, Phase = 1, from SPI0_CLK falling	P-1		P-2		P-3
			Polarity = 1, Phase = 0, from SPI0_CLK rising	0.5M+P-1		0.5M+P-2		0.5M+P-3
			Polarity = 1, Phase = 1, from SPI0_CLK rising	P-1		P-2		P-3

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(3) In the case where the master SPI is ready with new data before SPI0_SCS assertion.

(4) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].

(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted.

(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

(7) These parameters are in addition to the general timings for SPI master modes (Table 6-61).

Table 6-65 Additional SPI0 Master Timings, 5-Pin Option ⁽¹⁰⁾⁽¹⁾⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
18	t_{d(SPC_ENA)M}	Max delay for slave to deassert SPI0_ENA after final SPI0_CLK edge to ensure master does not begin the next transfer.⁽³⁾	Polarity = 0, Phase = 0, from SPI0_CLK falling		0.5M+P+5		0.5M+P+5		0.5M+P+6	ns
			Polarity = 0, Phase = 1, from SPI0_CLK falling		P+5		P+5		P+6
			Polarity = 1, Phase = 0, from SPI0_CLK rising		0.5M+P+5		0.5M+P+5		0.5M+P+6
			Polarity = 1, Phase = 1, from SPI0_CLK rising		P+5		P+5		P+6
20	t_{d(SPC_SCS)M}	Delay from final SPI0_CLK edge to master deasserting SPI0_SCS ⁽⁴⁾ ⁽⁵⁾	Polarity = 0, Phase = 0, from SPI0_CLK falling	0.5M+P-2		0.5M+P-2		0.5M+P-3		ns
			Polarity = 0, Phase = 1, from SPI0_CLK falling	P-2		P-2		P-3
			Polarity = 1, Phase = 0, from SPI0_CLK rising	0.5M+P-2		0.5M+P-2		0.5M+P-3
			Polarity = 1, Phase = 1, from SPI0_CLK rising	P-2		P-2		P-3
21	t_{d(SCSL_ENAL)M}	Max delay for slave SPI to drive SPI0_ENA valid after master asserts SPI0_SCS to delay the master from beginning the next transfer,			C2TDELAY+P		C2TDELAY+P		C2TDELAY+P	ns
22	t_{d(SCS_SPC)M}	Delay from SPI0_SCS active to first SPI0_CLK⁽⁶⁾ ⁽⁷⁾ ⁽⁸⁾	Polarity = 0, Phase = 0, to SPI0_CLK rising	2P-2		2P-2		2P-3		ns
			Polarity = 0, Phase = 1, to SPI0_CLK rising	0.5M+2P-2		0.5M+2P-2		0.5M+2P-3
			Polarity = 1, Phase = 0, to SPI0_CLK falling	2P-2		2P-2		2P-3
			Polarity = 1, Phase = 1, to SPI0_CLK falling	0.5M+2P-2		0.5M+2P-2		0.5M+2P-3
23	t_{d(ENA_SPC)M}	Delay from assertion of SPI0_ENA low to first SPI0_CLK edge.⁽⁹⁾	Polarity = 0, Phase = 0, to SPI0_CLK rising		3P+5		3P+5		3P+6	ns
			Polarity = 0, Phase = 1, to SPI0_CLK rising		0.5M+3P+5		0.5M+3P+5		0.5M+3P+6
			Polarity = 1, Phase = 0, to SPI0_CLK falling		3P+5		3P+5		3P+6
			Polarity = 1, Phase = 1, to SPI0_CLK falling		0.5M+3P+5		0.5M+3P+5		0.5M+3P+6

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(3) In the case where the master SPI is ready with new data before SPI0_ENA deassertion.

(4) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted.

(5) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

(6) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.

(7) In the case where the master SPI is ready with new data before SPI0_SCS assertion.

(8) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].

(9) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.

(10) These parameters are in addition to the general timings for SPI master modes (Table 6-62).

Table 6-66 Additional SPI0 Slave Timings, 4-Pin Enable Option ⁽³⁾⁽¹⁾⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
24	t_{d(SPC_ENAH)S}	Delay from final SPI0_CLK edge to slave deasserting SPI0_ENA.	Polarity = 0, Phase = 0, from SPI0_CLK falling	1.5P-3	2.5P+17.5	1.5P-3	2.5P+20	1.5P-3	2.5P+27	ns
			Polarity = 0, Phase = 1, from SPI0_CLK falling	– 0.5M+1.5P-3	– 0.5M+2.5P+17.5	– 0.5M+1.5P-3	– 0.5M+2.5P+20	– 0.5M+1.5P-3	– 0.5M+2.5P+27
			Polarity = 1, Phase = 0, from SPI0_CLK rising	1.5P-3	2.5P+17.5	1.5P-3	2.5P+20	1.5P-3	2.5P+27
			Polarity = 1, Phase = 1, from SPI0_CLK rising	– 0.5M+1.5P-3	– 0.5+2.5P+17.5	– 0.5M+1.5P-3	– 0.5+2.5P+20	– 0.5M+1.5P-3	– 0.5+2.5P+27

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

(3) These parameters are in addition to the general timings for SPI slave modes (Table 6-62).

Table 6-67 Additional SPI0 Slave Timings, 4-Pin Chip Select Option ⁽³⁾⁽¹⁾⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
25	t_{d(SCSL_SPC)S}	Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge at slave.		P + 1.5		P + 1.5		P + 1.5		ns
26	t_{d(SPC_SCSH)S}	Required delay from final SPI0_CLK edge before SPI0_SCS is deasserted.	Polarity = 0, Phase = 0, from SPI0_CLK falling	0.5M+P+4		0.5M+P+4		0.5M+P+5		ns
			Polarity = 0, Phase = 1, from SPI0_CLK falling	P+4		P+4		P+5
			Polarity = 1, Phase = 0, from SPI0_CLK rising	0.5M+P+4		0.5M+P+4		0.5M+P+5
			Polarity = 1, Phase = 1, from SPI0_CLK rising	P+4		P+4		P+5
27	t_{ena(SCSL_SOMI)S}	Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid			P+17.5		P+20		P+27	ns
28	t_{dis(SCSH_SOMI)S}	Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI			P+17.5		P+20		P+27	ns

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

(3) These parameters are in addition to the general timings for SPI slave modes (Table 6-62).

Table 6-68 Additional SPI0 Slave Timings, 5-Pin Option ⁽⁴⁾⁽¹⁾⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
25	t_{d(SCSL_SPC)S}	Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge at slave.		P + 1.5		P + 1.5		P + 1.5		ns
26	t_{d(SPC_SCSH)S}	Required delay from final SPI0_CLK edge before SPI0_SCS is deasserted.	Polarity = 0, Phase = 0, from SPI0_CLK falling	0.5M+P+4		0.5M+P+4		0.5M+P+5		ns
			Polarity = 0, Phase = 1, from SPI0_CLK falling	P+4		P+4		P+5
			Polarity = 1, Phase = 0, from SPI0_CLK rising	0.5M+P+4		0.5M+P+4		0.5M+P+5
			Polarity = 1, Phase = 1, from SPI0_CLK rising	P+4		P+4		P+5
27	t_{ena(SCSL_SOMI)S}	Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid			P+17.5		P+20		P+27	ns
28	t_{dis(SCSH_SOMI)S}	Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI			P+17.5		P+20		P+27	ns
29	t_{ena(SCSL_ENA)S}	Delay from master deasserting SPI0_SCS to slave driving SPI0_ENA valid			17.5		20		27	ns
30	t_{dis(SPC_ENA)S}	Delay from final clock receive edge on SPI0_CLK to slave 3-stating or driving high SPI0_ENA.⁽³⁾	Polarity = 0, Phase = 0, from SPI0_CLK falling		2.5P+17.5		2.5P+20		2.5P+27	ns
			Polarity = 0, Phase = 1, from SPI0_CLK rising		2.5P+17.5		2.5P+20		2.5P+27
			Polarity = 1, Phase = 0, from SPI0_CLK rising		2.5P+17.5		2.5P+20		2.5P+27
			Polarity = 1, Phase = 1, from SPI0_CLK falling		2.5P+17.5		2.5P+20		2.5P+27

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

(3) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.

(4) These parameters are in addition to the general timings for SPI slave modes (Table 6-62).

Table 6-69 General Timing Requirements for SPI1 Master Modes⁽¹⁾

NO.				1.3V, 1.2V		1.1V		1.0V		UNIT
NO.				MIN	MAX	MIN	MAX	MIN	MAX	UNIT
1	t_c(SPC)M	Cycle Time, SPI1_CLK, All Master Modes		20⁽²⁾	256P	30⁽²⁾	256P	40⁽²⁾	256P	ns
2	t_w(SPCH)M	Pulse Width High, SPI1_CLK, All Master Modes		0.5M-1		0.5M-1		0.5M-1		ns
3	t_w(SPCL)M	Pulse Width Low, SPI1_CLK, All Master Modes		0.5M-1		0.5M-1		0.5M-1		ns
4	t_{d(SIMO_SPC)M}	Delay, initial data bit valid on SPI1_SIMO to initial edge on SPI1_CLK⁽³⁾	Polarity = 0, Phase = 0, to SPI1_CLK rising		5		5		6	ns
			Polarity = 0, Phase = 1, to SPI1_CLK rising		-0.5M+5		-0.5M+5		-0.5M+6
			Polarity = 1, Phase = 0, to SPI1_CLK falling		5		5		6
			Polarity = 1, Phase = 1, to SPI1_CLK falling		-0.5M+5		-0.5M+5		-0.5M+6
5	t_{d(SPC_SIMO)M}	Delay, subsequent bits valid on SPI1_SIMO after transmit edge of SPI1_CLK	Polarity = 0, Phase = 0, from SPI1_CLK rising		5		5		6	ns
			Polarity = 0, Phase = 1, from SPI1_CLK falling		5		5		6
			Polarity = 1, Phase = 0, from SPI1_CLK falling		5		5		6
			Polarity = 1, Phase = 1, from SPI1_CLK rising		5		5		6
6	t_{oh(SPC_SIMO)M}	Output hold time, SPI1_SIMO valid after receive edge of SPI1_CLK	Polarity = 0, Phase = 0, from SPI1_CLK falling	0.5M-3		0.5M-3		0.5M-3		ns
			Polarity = 0, Phase = 1, from SPI1_CLK rising	0.5M-3		0.5M-3		0.5M-3
			Polarity = 1, Phase = 0, from SPI1_CLK rising	0.5M-3		0.5M-3		0.5M-3
			Polarity = 1, Phase = 1, from SPI1_CLK falling	0.5M-3		0.5M-3		0.5M-3
7	t_{su(SOMI_SPC)M}	Input Setup Time, SPI1_SOMI valid before receive edge of SPI1_CLK	Polarity = 0, Phase = 0, to SPI1_CLK falling	1.5		1.5		1.5		ns
			Polarity = 0, Phase = 1, to SPI1_CLK rising	1.5		1.5		1.5
			Polarity = 1, Phase = 0, to SPI1_CLK rising	1.5		1.5		1.5
			Polarity = 1, Phase = 1, to SPI1_CLK falling	1.5		1.5		1.5
8	t_{ih(SPC_SOMI)M}	Input Hold Time, SPI1_SOMI valid after receive edge of SPI1_CLK	Polarity = 0, Phase = 0, from SPI1_CLK falling	4		5		6		ns
			Polarity = 0, Phase = 1, from SPI1_CLK rising	4		5		6
			Polarity = 1, Phase = 0, from SPI1_CLK rising	4		5		6
			Polarity = 1, Phase = 1, from SPI1_CLK falling	4		5		6

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) This timing is limited by the timing shown or 3P, whichever is greater.

(3) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.

Table 6-70 General Timing Requirements for SPI1 Slave Modes⁽¹⁾

NO.				1.3V, 1.2V		1.1V		1.0V		UNIT
NO.				MIN	MAX	MIN	MAX	MIN	MAX	UNIT
9	t_c(SPC)S	Cycle Time, SPI1_CLK, All Slave Modes		40⁽²⁾		50⁽²⁾		60⁽²⁾		ns
10	t_w(SPCH)S	Pulse Width High, SPI1_CLK, All Slave Modes		18		22		27		ns
11	t_w(SPCL)S	Pulse Width Low, SPI1_CLK, All Slave Modes		18		22		27		ns
12	t_{su(SOMI_SPC)S}	Setup time, transmit data written to SPI before initial clock edge from master.⁽³⁾⁽⁴⁾	Polarity = 0, Phase = 0, to SPI1_CLK rising	2P		2P		2P		ns
			Polarity = 0, Phase = 1, to SPI1_CLK rising	2P		2P		2P
			Polarity = 1, Phase = 0, to SPI1_CLK falling	2P		2P		2P
			Polarity = 1, Phase = 1, to SPI1_CLK falling	2P		2P		2P
13	t_{d(SPC_SOMI)S}	Delay, subsequent bits valid on SPI1_SOMI after transmit edge of SPI1_CLK	Polarity = 0, Phase = 0, from SPI1_CLK rising		15		17		19	ns
			Polarity = 0, Phase = 1, from SPI1_CLK falling		15		17		19
			Polarity = 1, Phase = 0, from SPI1_CLK falling		15		17		19
			Polarity = 1, Phase = 1, from SPI1_CLK rising		15		17		19
14	t_{oh(SPC_SOMI)S}	Output hold time, SPI1_SOMI valid after receive edge of SPI1_CLK	Polarity = 0, Phase = 0, from SPI1_CLK falling	0.5S-4		0.5S-10		0.5S-12		ns
			Polarity = 0, Phase = 1, from SPI1_CLK rising	0.5S-4		0.5S-10		0.5S-12
			Polarity = 1, Phase = 0, from SPI1_CLK rising	0.5S-4		0.5S-10		0.5S-12
			Polarity = 1, Phase = 1, from SPI1_CLK falling	0.5S-4		0.5S-10		0.5S-12
15	t_{su(SIMO_SPC)S}	Input Setup Time, SPI1_SIMO valid before receive edge of SPI1_CLK	Polarity = 0, Phase = 0, to SPI1_CLK falling	1.5		1.5		1.5		ns
			Polarity = 0, Phase = 1, to SPI1_CLK rising	1.5		1.5		1.5
			Polarity = 1, Phase = 0, to SPI1_CLK rising	1.5		1.5		1.5
			Polarity = 1, Phase = 1, to SPI1_CLK falling	1.5		1.5		1.5
16	t_{ih(SPC_SIMO)S}	Input Hold Time, SPI1_SIMO valid after receive edge of SPI1_CLK	Polarity = 0, Phase = 0, from SPI1_CLK falling	4		5		6		ns
			Polarity = 0, Phase = 1, from SPI1_CLK rising	4		5		6
			Polarity = 1, Phase = 0, from SPI1_CLK rising	4		5		6
			Polarity = 1, Phase = 1, from SPI1_CLK falling	4		5		6

(1) P = SYSCLK2 period; S = t_c(SPC)S(SPI slave bit clock period)

(2) This timing is limited by the timing shown or 3P, whichever is greater.

(3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.

Table 6-71 Additional⁽⁵⁾ SPI1 Master Timings, 4-Pin Enable Option⁽¹⁾⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
17	t_{d(EN A_SPC)M}	Delay from slave assertion of SPI1_ENA active to first SPI1_CLK from master.⁽³⁾	Polarity = 0, Phase = 0, to SPI1_CLK rising		3P+5		3P+5		3P+6	ns
			Polarity = 0, Phase = 1, to SPI1_CLK rising		0.5M+3P+5		0.5M+3P+5		0.5M+3P+6
			Polarity = 1, Phase = 0, to SPI1_CLK falling		3P+5		3P+5		3P+6
			Polarity = 1, Phase = 1, to SPI1_CLK falling		0.5M+3P+5		0.5M+3P+5		0.5M+3P+6
18	t_{d(SPC_ENA)M}	Max delay for slave to deassert SPI1_ENA after final SPI1_CLK edge to ensure master does not begin the next transfer.⁽⁴⁾	Polarity = 0, Phase = 0, from SPI1_CLK falling		0.5M+P+5		0.5M+P+5		0.5M+P+6	ns
			Polarity = 0, Phase = 1, from SPI1_CLK falling		P+5		P+5		P+6
			Polarity = 1, Phase = 0, from SPI1_CLK rising		0.5M+P+5		0.5M+P+5		0.5M+P+6
			Polarity = 1, Phase = 1, from SPI1_CLK rising		P+5		P+5		P+6

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(3) In the case where the master SPI is ready with new data before SPI1_ENA assertion.

(4) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.

(5) These parameters are in addition to the general timings for SPI master modes (Table 6-69).

Table 6-72 Additional⁽⁷⁾ SPI1 Master Timings, 4-Pin Chip Select Option⁽¹⁾ ⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
19	t_{d(SCS_SPC)M}	Delay from SPI1_SCS active to first SPI1_CLK⁽³⁾ ⁽⁴⁾	Polarity = 0, Phase = 0, to SPI1_CLK rising	2P-1		2P-5		2P-6		ns
			Polarity = 0, Phase = 1, to SPI1_CLK rising	0.5M+2P-1		0.5M+2P-5		0.5M+2P-6
			Polarity = 1, Phase = 0, to SPI1_CLK falling	2P-1		2P-5		2P-6
			Polarity = 1, Phase = 1, to SPI1_CLK falling	0.5M+2P-1		0.5M+2P-5		0.5M+2P-6
20	t_{d(SPC_SCS)M}	Delay from final SPI1_CLK edge to master deasserting SPI1_SCS ⁽⁵⁾ ⁽⁶⁾	Polarity = 0, Phase = 0, from SPI1_CLK falling	0.5M+P-1		0.5M+P-5		0.5M+P-6		ns
			Polarity = 0, Phase = 1, from SPI1_CLK falling	P-1		P-5		P-6
			Polarity = 1, Phase = 0, from SPI1_CLK rising	0.5M+P-1		0.5M+P-5		0.5M+P-6
			Polarity = 1, Phase = 1, from SPI1_CLK rising	P-1		P-5		P-6

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(3) In the case where the master SPI is ready with new data before SPI1_SCS assertion.

(4) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].

(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted.

(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

(7) These parameters are in addition to the general timings for SPI master modes (Table 6-69).

Table 6-73 Additional⁽¹⁰⁾ SPI1 Master Timings, 5-Pin Option⁽¹⁾⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
18	t_{d(SPC_ENA)M}	Max delay for slave to deassert SPI1_ENA after final SPI1_CLK edge to ensure master does not begin the next transfer.⁽³⁾	Polarity = 0, Phase = 0, from SPI1_CLK falling		0.5M+P+5		0.5M+P+5		0.5M+P+6	ns
			Polarity = 0, Phase = 1, from SPI1_CLK falling		P+5		P+5		P+6
			Polarity = 1, Phase = 0, from SPI1_CLK rising		0.5M+P+5		0.5M+P+5		0.5M+P+6
			Polarity = 1, Phase = 1, from SPI1_CLK rising		P+5		P+5		P+6
20	t_{d(SPC_SCS)M}	Delay from final SPI1_CLK edge to master deasserting SPI1_SCS ⁽⁴⁾⁽⁵⁾	Polarity = 0, Phase = 0, from SPI1_CLK falling	0.5M+P-1		0.5M+P-5		0.5M+P-6		ns
			Polarity = 0, Phase = 1, from SPI1_CLK falling	P-1		P-5		P-6
			Polarity = 1, Phase = 0, from SPI1_CLK rising	0.5M+P-1		0.5M+P-5		0.5M+P-6
			Polarity = 1, Phase = 1, from SPI1_CLK rising	P-1		P-5		P-6
21	t_{d(SCSL_ENAL)M}	Max delay for slave SPI to drive SPI1_ENA valid after master asserts SPI1_SCS to delay the master from beginning the next transfer,		C2TDELAY+P		C2TDELAY+P		C2TDELAY+P		ns
22	t_{d(SCS_SPC)M}	Delay from SPI1_SCS active to first SPI1_CLK⁽⁶⁾⁽⁷⁾⁽⁸⁾	Polarity = 0, Phase = 0, to SPI1_CLK rising	2P-1		2P-5		2P-6		ns
			Polarity = 0, Phase = 1, to SPI1_CLK rising	0.5M+2P-1		0.5M+2P-5		0.5M+2P-6
			Polarity = 1, Phase = 0, to SPI1_CLK falling	2P-1		2P-5		2P-6
			Polarity = 1, Phase = 1, to SPI1_CLK falling	0.5M+2P-1		0.5M+2P-5		0.5M+2P-6
23	t_{d(ENA_SPC)M}	Delay from assertion of SPI1_ENA low to first SPI1_CLK edge.⁽⁹⁾	Polarity = 0, Phase = 0, to SPI1_CLK rising		3P+5		3P+5		3P+6	ns
			Polarity = 0, Phase = 1, to SPI1_CLK rising	0.5M+3P+5		0.5M+3P+5		0.5M+3P+6
			Polarity = 1, Phase = 0, to SPI1_CLK falling		3P+5		3P+5		3P+6
			Polarity = 1, Phase = 1, to SPI1_CLK falling	0.5M+3P+5		0.5M+3P+5		0.5M+3P+6

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(3) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.

(4) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted.

(5) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

(6) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.

(7) In the case where the master SPI is ready with new data before SPI1_SCS assertion.

(8) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].

(9) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.

(10) These parameters are in addition to the general timings for SPI master modes (Table 6-70).

Table 6-74 Additional⁽³⁾ SPI1 Slave Timings, 4-Pin Enable Option⁽¹⁾⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
24	t_{d(SPC_ENAH)S}	Delay from final SPI1_CLK edge to slave deasserting SPI1_ENA.	Polarity = 0, Phase = 0, from SPI1_CLK falling	1.5P-3	2.5P+15	1.5P-10	2.5P+17	1.5P-12	2.5P+19	ns
			Polarity = 0, Phase = 1, from SPI1_CLK falling	–0.5M+1.5P-3	–0.5M+2.5P+15	–0.5M+1.5P-10	–0.5M+2.5P+17	–0.5M+1.5P-12	–0.5M+2.5P+19
			Polarity = 1, Phase = 0, from SPI1_CLK rising	1.5P-3	2.5P+15	1.5P-10	2.5P+17	1.5P-12	2.5P+19
			Polarity = 1, Phase = 1, from SPI1_CLK rising	–0.5M+1.5P-3	–0.5M+2.5P+15	–0.5M+1.5P-10	–0.5M+2.5P+17	–0.5M+1.5P-12	–0.5M+2.5P+19

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

(3) These parameters are in addition to the general timings for SPI slave modes (Table 6-70).

Table 6-75 Additional⁽³⁾ SPI1 Slave Timings, 4-Pin Chip Select Option⁽¹⁾⁽²⁾

NO.	PARAMETER			1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
25	t_{d(SCSL_SPC)S}	Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave.		P+1.5		P+1.5		P+1.5		ns
26	t_{d(SPC_SCSH)S}	Required delay from final SPI1_CLK edge before SPI1_SCS is deasserted.	Polarity = 0, Phase = 0, from SPI1_CLK falling	0.5M+P+4		0.5M+P+5		0.5M+P+6		ns
			Polarity = 0, Phase = 1, from SPI1_CLK falling	P+4		P+5		P+6
			Polarity = 1, Phase = 0, from SPI1_CLK rising	0.5M+P+4		0.5M+P+5		0.5M+P+6
			Polarity = 1, Phase = 1, from SPI1_CLK rising	P+4		P+5		P+6
27	t_{ena(SCSL_SOMI)S}	Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid			P+15		P+17		P+19	ns
28	t_{dis(SCSH_SOMI)S}	Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI			P+15		P+17		P+19	ns

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

(3) These parameters are in addition to the general timings for SPI slave modes (Table 6-70).

Table 6-76 Additional⁽⁴⁾ SPI1 Slave Timings, 5-Pin Option⁽¹⁾⁽²⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
25	t_{d(SCSL_SPC)S}	Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave.		P+1.5		P+1.5		P+1.5		ns
26	t_{d(SPC_SCSH)S}	Required delay from final SPI1_CLK edge before SPI1_SCS is deasserted.	Polarity = 0, Phase = 0, from SPI1_CLK falling	0.5M+P+4		0.5M+P+5		0.5M+P+6		ns
			Polarity = 0, Phase = 1, from SPI1_CLK falling	P+4		P+5		P+6
			Polarity = 1, Phase = 0, from SPI1_CLK rising	0.5M+P+4		0.5M+P+5		0.5M+P+6
			Polarity = 1, Phase = 1, from SPI1_CLK rising	P+4		P+5		P+6
27	t_{ena(SCSL_SOMI)S}	Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid			P+15		P+17		P+19	ns
28	t_{dis(SCSH_SOMI)S}	Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI			P+15		P+17		P+19	ns
29	t_{ena(SCSL_ENA)S}	Delay from master deasserting SPI1_SCS to slave driving SPI1_ENA valid			15		17		19	ns
30	t_{dis(SPC_ENA)S}	Delay from final clock receive edge on SPI1_CLK to slave 3-stating or driving high SPI1_ENA.⁽³⁾	Polarity = 0, Phase = 0, from SPI1_CLK falling		2.5P+15		2.5P+17		2.5P+19	ns
			Polarity = 0, Phase = 1, from SPI1_CLK rising		2.5P+15		2.5P+17		2.5P+19
			Polarity = 1, Phase = 0, from SPI1_CLK rising		2.5P+15		2.5P+17		2.5P+19
			Polarity = 1, Phase = 1, from SPI1_CLK falling		2.5P+15		2.5P+17		2.5P+19

(1) P = SYSCLK2 period; M = t_c(SPC)M(SPI master bit clock period)

(2) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.

(3) SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.

(4) These parameters are in addition to the general timings for SPI slave modes (Table 6-70).

Figure 6-37 SPI Timings—Master Mode

Figure 6-38 SPI Timings—Slave Mode

Figure 6-39 SPI Timings—Master Mode (4-Pin and 5-Pin)

Figure 6-40 SPI Timings—Slave Mode (4-Pin and 5-Pin)

6.17 Inter-Integrated Circuit Serial Ports (I2C)

6.17.1 I2C Device-Specific Information

Each I2C port supports:

Compatible with Philips® I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to Remove Noise 50 ns or less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
General-Purpose I/O Capability if not used as I2C

Figure 6-41 is block diagram of the device I2C Module.

Figure 6-41 I2C Module Block Diagram

6.17.2 I2C Peripheral Registers Description(s)

Table 6-77 is the list of the I2C registers.

Table 6-77 Inter-Integrated Circuit (I2C) Registers

I2C0 BYTE ADDRESS	I2C1 BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01C2 2000	0x01E2 8000	ICOAR	I2C Own Address Register
0x01C2 2004	0x01E2 8004	ICIMR	I2C Interrupt Mask Register
0x01C2 2008	0x01E2 8008	ICSTR	I2C Interrupt Status Register
0x01C2 200C	0x01E2 800C	ICCLKL	I2C Clock Low-Time Divider Register
0x01C2 2010	0x01E2 8010	ICCLKH	I2C Clock High-Time Divider Register
0x01C2 2014	0x01E2 8014	ICCNT	I2C Data Count Register
0x01C2 2018	0x01E2 8018	ICDRR	I2C Data Receive Register
0x01C2 201C	0x01E2 801C	ICSAR	I2C Slave Address Register
0x01C2 2020	0x01E2 8020	ICDXR	I2C Data Transmit Register
0x01C2 2024	0x01E2 8024	ICMDR	I2C Mode Register
0x01C2 2028	0x01E2 8028	ICIVR	I2C Interrupt Vector Register
0x01C2 202C	0x01E2 802C	ICEMDR	I2C Extended Mode Register
0x01C2 2030	0x01E2 8030	ICPSC	I2C Prescaler Register
0x01C2 2034	0x01E2 8034	REVID1	I2C Revision Identification Register 1
0x01C2 2038	0x01E2 8038	REVID2	I2C Revision Identification Register 2
0x01C2 2048	0x01E2 8048	ICPFUNC	I2C Pin Function Register
0x01C2 204C	0x01E2 804C	ICPDIR	I2C Pin Direction Register
0x01C2 2050	0x01E2 8050	ICPDIN	I2C Pin Data In Register
0x01C2 2054	0x01E2 8054	ICPDOUT	I2C Pin Data Out Register
0x01C2 2058	0x01E2 8058	ICPDSET	I2C Pin Data Set Register
0x01C2 205C	0x01E2 805C	ICPDCLR	I2C Pin Data Clear Register

6.17.3 I2C Electrical Data/Timing

6.17.3.1 Inter-Integrated Circuit (I2C) Timing

Table 6-78 and Table 6-79 assume testing over recommended operating conditions (see Figure 6-42 and Figure 6-43).

Table 6-78 Timing Requirements for I2C Input

NO.			1.3V, 1.2V, 1.1V, 1.0V				UNIT
			Standard Mode		Fast Mode
			MIN	MAX	MIN	MAX
1	t_c(SCL)	Cycle time, I2Cx_SCL	10		2.5		μs
2	t_{su(SCLH-SDAL)}	Setup time, I2Cx_SCL high before I2Cx_SDA low	4.7		0.6		μs
3	t_h(SCLL-SDAL)	Hold time, I2Cx_SCL low after I2Cx_SDA low	4		0.6		μs
4	t_w(SCLL)	Pulse duration, I2Cx_SCL low	4.7		1.3		μs
5	t_w(SCLH)	Pulse duration, I2Cx_SCL high	4		0.6		μs
6	t_su(SDA-SCLH)	Setup time, I2Cx_SDA before I2Cx_SCL high	250		100		ns
7	t_h(SDA-SCLL)	Hold time, I2Cx_SDA after I2Cx_SCL low	0		0	0.9	μs
8	t_w(SDAH)	Pulse duration, I2Cx_SDA high	4.7		1.3		μs
9	t_r(SDA)	Rise time, I2Cx_SDA		1000	20 + 0.1C_b	300	ns
10	t_r(SCL)	Rise time, I2Cx_SCL		1000	20 + 0.1C_b	300	ns
11	t_f(SDA)	Fall time, I2Cx_SDA		300	20 + 0.1C_b	300	ns
12	t_f(SCL)	Fall time, I2Cx_SCL		300	20 + 0.1C_b	300	ns
13	t_{su(SCLH-SDAH)}	Setup time, I2Cx_SCL high before I2Cx_SDA high	4		0.6		μs
14	t_w(SP)	Pulse duration, spike (must be suppressed)	N/A		0	50	ns
15	C_b	Capacitive load for each bus line		400		400	pF

Table 6-79 Switching Characteristics for I2C ⁽¹⁾

NO.	PARAMETER		1.3V, 1.2V, 1.1V, 1.0V				UNIT
			Standard Mode		Fast Mode
			MIN	MAX	MIN	MAX
16	t_c(SCL)	Cycle time, I2Cx_SCL	10		2.5		μs
17	t_{su(SCLH-SDAL)}	Setup time, I2Cx_SCL high before I2Cx_SDA low	4.7		0.6		μs
18	t_h(SDAL-SCLL)	Hold time, I2Cx_SCL low after I2Cx_SDA low	4		0.6		μs
19	t_w(SCLL)	Pulse duration, I2Cx_SCL low	4.7		1.3		μs
20	t_w(SCLH)	Pulse duration, I2Cx_SCL high	4		0.6		μs
21	t_{su(SDAV-SCLH)}	Setup time, I2Cx_SDA valid before I2Cx_SCL high	250		100		ns
22	t_h(SCLL-SDAV)	Hold time, I2Cx_SDA valid after I2Cx_SCL low	0		0	0.9	μs
23	t_w(SDAH)	Pulse duration, I2Cx_SDA high	4.7		1.3		μs
28	t_{su(SCLH-SDAH)}	Setup time, I2Cx_SCL high before I2Cx_SDA high	4		0.6		μs

(1) I2C must be configured correctly to meet the timings in Table 6-79.

Figure 6-42 I2C Receive Timings

Figure 6-43 I2C Transmit Timings

6.18 Universal Asynchronous Receiver/Transmitter (UART)

Each UART has the following features:

16-byte storage space for both the transmitter and receiver FIFOs
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
DMA signaling capability for both received and transmitted data
Programmable auto-rts and auto-cts for autoflow control
Programmable Baud Rate up to 12 MBaud
Programmable Oversampling Options of x13 and x16
Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
Prioritized interrupts
Programmable serial data formats
- 5, 6, 7, or 8-bit characters
- Even, odd, or no parity bit generation and detection
- 1, 1.5, or 2 stop bit generation
False start bit detection
Line break generation and detection
Internal diagnostic capabilities
- Loopback controls for communications link fault isolation
- Break, parity, overrun, and framing error simulation
Modem control functions (CTS, RTS)

The UART registers are listed in Section 6.18.1

6.18.1 UART Peripheral Registers Description(s)

Table 6-80 is the list of UART registers.

Table 6-80 UART Registers

UART0 BYTE ADDRESS	UART1 BYTE ADDRESS	UART2 BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01C4 2000	0x01D0 C000	0x01D0 D000	RBR	Receiver Buffer Register (read only)
0x01C4 2000	0x01D0 C000	0x01D0 D000	THR	Transmitter Holding Register (write only)
0x01C4 2004	0x01D0 C004	0x01D0 D004	IER	Interrupt Enable Register
0x01C4 2008	0x01D0 C008	0x01D0 D008	IIR	Interrupt Identification Register (read only)
0x01C4 2008	0x01D0 C008	0x01D0 D008	FCR	FIFO Control Register (write only)
0x01C4 200C	0x01D0 C00C	0x01D0 D00C	LCR	Line Control Register
0x01C4 2010	0x01D0 C010	0x01D0 D010	MCR	Modem Control Register
0x01C4 2014	0x01D0 C014	0x01D0 D014	LSR	Line Status Register
0x01C4 2018	0x01D0 C018	0x01D0 D018	MSR	Modem Status Register
0x01C4 201C	0x01D0 C01C	0x01D0 D01C	SCR	Scratchpad Register
0x01C4 2020	0x01D0 C020	0x01D0 D020	DLL	Divisor LSB Latch
0x01C4 2024	0x01D0 C024	0x01D0 D024	DLH	Divisor MSB Latch
0x01C4 2028	0x01D0 C028	0x01D0 D028	REVID1	Revision Identification Register 1
0x01C4 2030	0x01D0 C030	0x01D0 D030	PWREMU_MGMT	Power and Emulation Management Register
0x01C4 2034	0x01D0 C034	0x01D0 D034	MDR	Mode Definition Register

6.18.2 UART Electrical Data/Timing

Table 6-81 Timing Requirements for UART Receive⁽¹⁾ (see Figure 6-44)

NO.			1.3V, 1.2V, 1.1V, 1.0V		UNIT
NO.			MIN	MAX	UNIT
4	t_w(URXDB)	Pulse duration, receive data bit (RXDn)	0.96U	1.05U	ns
5	t_w(URXSB)	Pulse duration, receive start bit	0.96U	1.05U	ns

(1) U = UART baud time = 1/programmed baud rate.

Table 6-82 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit⁽¹⁾
(see Figure 6-44)

NO.	PARAMETER		1.3V, 1.2V, 1.1V, 1.0V		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
1	f_(baud)	Maximum programmable baud rate		D/E ⁽²⁾ ⁽³⁾	MBaud ⁽⁴⁾
2	t_w(UTXDB)	Pulse duration, transmit data bit (TXDn)	U - 2	U + 2	ns
3	t_w(UTXSB)	Pulse duration, transmit start bit	U - 2	U + 2	ns

(1) U = UART baud time = 1/programmed baud rate.

(2) D = UART input clock in MHz.
For UART0, the UART input clock is SYSCLK2.
For UART1 or UART2, the UART input clock is ASYNC3 (either PLL0_SYCLK2 or PLL1_SYSCLK2).

(3) E = UART divisor x UART sampling rate. The UART divisor is set through the UART divisor latch registers (DLL and DLH). The UART sampling rate is set through the over-sampling mode select bit (OSM_SEL) of the UART mode definition register (MDR).

(4) Baud rate is not indicative of data rate. Actual data rate will be limited by system factors such as EDMA loading, EMIF/DDR loading, system frequency, etc.

Figure 6-44 UART Transmit/Receive Timing

6.19 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]

The USB2.0 peripheral supports the following features:

USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s)
USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)
All transfer modes (control, bulk, interrupt, and isochronous)
4 Transmit (TX) and 4 Receive (RX) endpoints in addition to endpoint 0
FIFO RAM
- 4K endpoint
- Programmable size
Integrated USB 2.0 High Speed PHY
Connects to a standard Charge Pump for VBUS 5 V generation
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB

Important Notice: The USB0 controller module clock (PLL0_SYSCLK2) must be greater than 30 MHz for proper operation of the USB controller. A clock rate of 60 MHz or greater is recommended to avoid data throughput reduction.

Table 6-83 is the list of USB OTG registers.

Table 6-83 Universal Serial Bus OTG (USB0) Registers

BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01E0 0000	REVID	Revision Register
0x01E0 0004	CTRLR	Control Register
0x01E0 0008	STATR	Status Register
0x01E0 000C	EMUR	Emulation Register
0x01E0 0010	MODE	Mode Register
0x01E0 0014	AUTOREQ	Autorequest Register
0x01E0 0018	SRPFIXTIME	SRP Fix Time Register
0x01E0 001C	TEARDOWN	Teardown Register
0x01E0 0020	INTSRCR	USB Interrupt Source Register
0x01E0 0024	INTSETR	USB Interrupt Source Set Register
0x01E0 0028	INTCLRR	USB Interrupt Source Clear Register
0x01E0 002C	INTMSKR	USB Interrupt Mask Register
0x01E0 0030	INTMSKSETR	USB Interrupt Mask Set Register
0x01E0 0034	INTMSKCLRR	USB Interrupt Mask Clear Register
0x01E0 0038	INTMASKEDR	USB Interrupt Source Masked Register
0x01E0 003C	EOIR	USB End of Interrupt Register
0x01E0 0040	-	Reserved
0x01E0 0050	GENRNDISSZ1	Generic RNDIS Size EP1
0x01E0 0054	GENRNDISSZ2	Generic RNDIS Size EP2
0x01E0 0058	GENRNDISSZ3	Generic RNDIS Size EP3
0x01E0 005C	GENRNDISSZ4	Generic RNDIS Size EP4
0x01E0 0400	FADDR	Function Address Register
0x01E0 0401	POWER	Power Management Register
0x01E0 0402	INTRTX	Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
0x01E0 0404	INTRRX	Interrupt Register for Receive Endpoints 1 to 4
0x01E0 0406	INTRTXE	Interrupt enable register for INTRTX
0x01E0 0408	INTRRXE	Interrupt Enable Register for INTRRX
0x01E0 040A	INTRUSB	Interrupt Register for Common USB Interrupts
0x01E0 040B	INTRUSBE	Interrupt Enable Register for INTRUSB
0x01E0 040C	FRAME	Frame Number Register
0x01E0 040E	INDEX	Index Register for Selecting the Endpoint Status and Control Registers
0x01E0 040F	TESTMODE	Register to Enable the USB 2.0 Test Modes
Indexed Registers These registers operate on the endpoint selected by the INDEX register
0x01E0 0410	TXMAXP	Maximum Packet Size for Peripheral/Host Transmit Endpoint (Index register set to select Endpoints 1-4 only)
0x01E0 0412	PERI_CSR0	Control Status Register for Endpoint 0 in Peripheral Mode. (Index register set to select Endpoint 0)
	HOST_CSR0	Control Status Register for Endpoint 0 in Host Mode. (Index register set to select Endpoint 0)
	PERI_TXCSR	Control Status Register for Peripheral Transmit Endpoint. (Index register set to select Endpoints 1-4)
	HOST_TXCSR	Control Status Register for Host Transmit Endpoint. (Index register set to select Endpoints 1-4)
0x01E0 0414	RXMAXP	Maximum Packet Size for Peripheral/Host Receive Endpoint (Index register set to select Endpoints 1-4 only)
0x01E0 0416	PERI_RXCSR	Control Status Register for Peripheral Receive Endpoint. (Index register set to select Endpoints 1-4)
0x01E0 0416	HOST_RXCSR	Control Status Register for Host Receive Endpoint. (Index register set to select Endpoints 1-4)
0x01E0 0418	COUNT0	Number of Received Bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0)
0x01E0 0418	RXCOUNT	Number of Bytes in Host Receive Endpoint FIFO. (Index register set to select Endpoints 1- 4)
0x01E0 041A	HOST_TYPE0	Defines the speed of Endpoint 0
0x01E0 041A	HOST_TXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. (Index register set to select Endpoints 1-4 only)
0x01E0 041B	HOST_NAKLIMIT0	Sets the NAK response timeout on Endpoint 0. (Index register set to select Endpoint 0)
0x01E0 041B	HOST_TXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. (Index register set to select Endpoints 1-4 only)
0x01E0 041C	HOST_RXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. (Index register set to select Endpoints 1-4 only)
0x01E0 041D	HOST_RXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. (Index register set to select Endpoints 1-4 only)
0x01E0 041F	CONFIGDATA	Returns details of core configuration. (Index register set to select Endpoint 0)
FIFO
0x01E0 0420	FIFO0	Transmit and Receive FIFO Register for Endpoint 0
0x01E0 0424	FIFO1	Transmit and Receive FIFO Register for Endpoint 1
0x01E0 0428	FIFO2	Transmit and Receive FIFO Register for Endpoint 2
0x01E0 042C	FIFO3	Transmit and Receive FIFO Register for Endpoint 3
0x01E0 0430	FIFO4	Transmit and Receive FIFO Register for Endpoint 4
OTG Device Control
0x01E0 0460	DEVCTL	Device Control Register
Dynamic FIFO Control
0x01E0 0462	TXFIFOSZ	Transmit Endpoint FIFO Size (Index register set to select Endpoints 1-4 only)
0x01E0 0463	RXFIFOSZ	Receive Endpoint FIFO Size (Index register set to select Endpoints 1-4 only)
0x01E0 0464	TXFIFOADDR	Transmit Endpoint FIFO Address (Index register set to select Endpoints 1-4 only)
0x01E0 0466	RXFIFOADDR	Receive Endpoint FIFO Address (Index register set to select Endpoints 1-4 only)
0x01E0 046C	HWVERS	Hardware Version Register
Target Endpoint 0 Control Registers, Valid Only in Host Mode
0x01E0 0480	TXFUNCADDR	Address of the target function that has to be accessed through the associated Transmit Endpoint.
0x01E0 0482	TXHUBADDR	Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0483	TXHUBPORT	Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0484	RXFUNCADDR	Address of the target function that has to be accessed through the associated Receive Endpoint.
0x01E0 0486	RXHUBADDR	Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0487	RXHUBPORT	Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 1 Control Registers, Valid Only in Host Mode
0x01E0 0488	TXFUNCADDR	Address of the target function that has to be accessed through the associated Transmit Endpoint.
0x01E0 048A	TXHUBADDR	Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 048B	TXHUBPORT	Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 048C	RXFUNCADDR	Address of the target function that has to be accessed through the associated Receive Endpoint.
0x01E0 048E	RXHUBADDR	Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 048F	RXHUBPORT	Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 2 Control Registers, Valid Only in Host Mode
0x01E0 0490	TXFUNCADDR	Address of the target function that has to be accessed through the associated Transmit Endpoint.
0x01E0 0492	TXHUBADDR	Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0493	TXHUBPORT	Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0494	RXFUNCADDR	Address of the target function that has to be accessed through the associated Receive Endpoint.
0x01E0 0496	RXHUBADDR	Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0497	RXHUBPORT	Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 3 Control Registers, Valid Only in Host Mode
0x01E0 0498	TXFUNCADDR	Address of the target function that has to be accessed through the associated Transmit Endpoint.
0x01E0 049A	TXHUBADDR	Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 049B	TXHUBPORT	Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 049C	RXFUNCADDR	Address of the target function that has to be accessed through the associated Receive Endpoint.
0x01E0 049E	RXHUBADDR	Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 049F	RXHUBPORT	Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Target Endpoint 4 Control Registers, Valid Only in Host Mode
0x01E0 04A0	TXFUNCADDR	Address of the target function that has to be accessed through the associated Transmit Endpoint.
0x01E0 04A2	TXHUBADDR	Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 04A3	TXHUBPORT	Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 04A4	RXFUNCADDR	Address of the target function that has to be accessed through the associated Receive Endpoint.
0x01E0 04A6	RXHUBADDR	Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 04A7	RXHUBPORT	Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Control and Status Register for Endpoint 0
0x01E0 0502	PERI_CSR0	Control Status Register for Endpoint 0 in Peripheral Mode
	HOST_CSR0	Control Status Register for Endpoint 0 in Host Mode
0x01E0 0508	COUNT0	Number of Received Bytes in Endpoint 0 FIFO
0x01E0 050A	HOST_TYPE0	Defines the Speed of Endpoint 0
0x01E0 050B	HOST_NAKLIMIT0	Sets the NAK Response Timeout on Endpoint 0
0x01E0 050F	CONFIGDATA	Returns details of core configuration.
Control and Status Register for Endpoint 1
0x01E0 0510	TXMAXP	Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0512	PERI_TXCSR	Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
0x01E0 0512	HOST_TXCSR	Control Status Register for Host Transmit Endpoint (host mode)
0x01E0 0514	RXMAXP	Maximum Packet Size for Peripheral/Host Receive Endpoint
0x01E0 0516	PERI_RXCSR	Control Status Register for Peripheral Receive Endpoint (peripheral mode)
0x01E0 0516	HOST_RXCSR	Control Status Register for Host Receive Endpoint (host mode)
0x01E0 0518	RXCOUNT	Number of Bytes in Host Receive endpoint FIFO
0x01E0 051A	HOST_TXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint.
0x01E0 051B	HOST_TXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint.
0x01E0 051C	HOST_RXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint.
0x01E0 051D	HOST_RXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint.
Control and Status Register for Endpoint 2
0x01E0 0520	TXMAXP	Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0522	PERI_TXCSR	Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
0x01E0 0522	HOST_TXCSR	Control Status Register for Host Transmit Endpoint (host mode)
0x01E0 0524	RXMAXP	Maximum Packet Size for Peripheral/Host Receive Endpoint
0x01E0 0526	PERI_RXCSR	Control Status Register for Peripheral Receive Endpoint (peripheral mode)
0x01E0 0526	HOST_RXCSR	Control Status Register for Host Receive Endpoint (host mode)
0x01E0 0528	RXCOUNT	Number of Bytes in Host Receive endpoint FIFO
0x01E0 052A	HOST_TXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint.
0x01E0 052B	HOST_TXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint.
0x01E0 052C	HOST_RXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint.
0x01E0 052D	HOST_RXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint.
Control and Status Register for Endpoint 3
0x01E0 0530	TXMAXP	Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0532	PERI_TXCSR	Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
0x01E0 0532	HOST_TXCSR	Control Status Register for Host Transmit Endpoint (host mode)
0x01E0 0534	RXMAXP	Maximum Packet Size for Peripheral/Host Receive Endpoint
0x01E0 0536	PERI_RXCSR	Control Status Register for Peripheral Receive Endpoint (peripheral mode)
0x01E0 0536	HOST_RXCSR	Control Status Register for Host Receive Endpoint (host mode)
0x01E0 0538	RXCOUNT	Number of Bytes in Host Receive endpoint FIFO
0x01E0 053A	HOST_TXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint.
0x01E0 053B	HOST_TXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint.
0x01E0 053C	HOST_RXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint.
0x01E0 053D	HOST_RXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint.
Control and Status Register for Endpoint 4
0x01E0 0540	TXMAXP	Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0542	PERI_TXCSR	Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
0x01E0 0542	HOST_TXCSR	Control Status Register for Host Transmit Endpoint (host mode)
0x01E0 0544	RXMAXP	Maximum Packet Size for Peripheral/Host Receive Endpoint
0x01E0 0546	PERI_RXCSR	Control Status Register for Peripheral Receive Endpoint (peripheral mode)
0x01E0 0546	HOST_RXCSR	Control Status Register for Host Receive Endpoint (host mode)
0x01E0 0548	RXCOUNT	Number of Bytes in Host Receive endpoint FIFO
0x01E0 054A	HOST_TXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint.
0x01E0 054B	HOST_TXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint.
0x01E0 054C	HOST_RXTYPE	Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint.
0x01E0 054D	HOST_RXINTERVAL	Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint.
DMA Registers
0x01E0 1000	DMAREVID	DMA Revision Register
0x01E0 1004	TDFDQ	DMA Teardown Free Descriptor Queue Control Register
0x01E0 1008	DMAEMU	DMA Emulation Control Register
0x01E0 1800	TXGCR[0]	Transmit Channel 0 Global Configuration Register
0x01E0 1808	RXGCR[0]	Receive Channel 0 Global Configuration Register
0x01E0 180C	RXHPCRA[0]	Receive Channel 0 Host Packet Configuration Register A
0x01E0 1810	RXHPCRB[0]	Receive Channel 0 Host Packet Configuration Register B
0x01E0 1820	TXGCR[1]	Transmit Channel 1 Global Configuration Register
0x01E0 1828	RXGCR[1]	Receive Channel 1 Global Configuration Register
0x01E0 182C	RXHPCRA[1]	Receive Channel 1 Host Packet Configuration Register A
0x01E0 1830	RXHPCRB[1]	Receive Channel 1 Host Packet Configuration Register B
0x01E0 1840	TXGCR[2]	Transmit Channel 2 Global Configuration Register
0x01E0 1848	RXGCR[2]	Receive Channel 2 Global Configuration Register
0x01E0 184C	RXHPCRA[2]	Receive Channel 2 Host Packet Configuration Register A
0x01E0 1850	RXHPCRB[2]	Receive Channel 2 Host Packet Configuration Register B
0x01E0 1860	TXGCR[3]	Transmit Channel 3 Global Configuration Register
0x01E0 1868	RXGCR[3]	Receive Channel 3 Global Configuration Register
0x01E0 186C	RXHPCRA[3]	Receive Channel 3 Host Packet Configuration Register A
0x01E0 1870	RXHPCRB[3]	Receive Channel 3 Host Packet Configuration Register B
0x01E0 2000	DMA_SCHED_CTRL	DMA Scheduler Control Register
0x01E0 2800	WORD[0]	DMA Scheduler Table Word 0
0x01E0 2804	WORD[1]	DMA Scheduler Table Word 1
. . .	. . .	. . .
0x01E0 28FC	WORD[63]	DMA Scheduler Table Word 63
Queue Manager Registers
0x01E0 4000	QMGRREVID	Queue Manager Revision Register
0x01E0 4008	DIVERSION	Queue Diversion Register
0x01E0 4020	FDBSC0	Free Descriptor/Buffer Starvation Count Register 0
0x01E0 4024	FDBSC1	Free Descriptor/Buffer Starvation Count Register 1
0x01E0 4028	FDBSC2	Free Descriptor/Buffer Starvation Count Register 2
0x01E0 402C	FDBSC3	Free Descriptor/Buffer Starvation Count Register 3
0x01E0 4080	LRAM0BASE	Linking RAM Region 0 Base Address Register
0x01E0 4084	LRAM0SIZE	Linking RAM Region 0 Size Register
0x01E0 4088	LRAM1BASE	Linking RAM Region 1 Base Address Register
0x01E0 4090	PEND0	Queue Pending Register 0
0x01E0 4094	PEND1	Queue Pending Register 1
0x01E0 5000	QMEMRBASE[0]	Memory Region 0 Base Address Register
0x01E0 5004	QMEMRCTRL[0]	Memory Region 0 Control Register
0x01E0 5010	QMEMRBASE[1]	Memory Region 1 Base Address Register
0x01E0 5014	QMEMRCTRL[1]	Memory Region 1 Control Register
. . .	. . .	. . .
0x01E0 50F0	QMEMRBASE[15]	Memory Region 15 Base Address Register
0x01E0 50F4	QMEMRCTRL[15]	Memory Region 15 Control Register
0x01E0 600C	CTRLD[0]	Queue Manager Queue 0 Control Register D
0x01E0 601C	CTRLD[1]	Queue Manager Queue 1 Control Register D
. . .	. . .	. . .
0x01E0 63FC	CTRLD[63]	Queue Manager Queue 63 Status Register D
0x01E0 6800	QSTATA[0]	Queue Manager Queue 0 Status Register A
0x01E0 6804	QSTATB[0]	Queue Manager Queue 0 Status Register B
0x01E0 6808	QSTATC[0]	Queue Manager Queue 0 Status Register C
0x01E0 6810	QSTATA[1]	Queue Manager Queue 1 Status Register A
0x01E0 6814	QSTATB[1]	Queue Manager Queue 1 Status Register B
0x01E0 6818	QSTATC[1]	Queue Manager Queue 1 Status Register C
. . .	. . .	. . .
0x01E0 6BF0	QSTATA[63]	Queue Manager Queue 63 Status Register A
0x01E0 6BF4	QSTATB[63]	Queue Manager Queue 63 Status Register B
0x01E0 6BF8	QSTATC[63]	Queue Manager Queue 63 Status Register C

6.19.1 USB0 [USB2.0] Electrical Data/Timing

The USB PHY PLL can support input clock of the following frequencies: 12.0 MHz, 13.0 MHz, 19.2 MHz, 20.0 MHz, 24.0 MHz, 26.0 MHz, 38.4 MHz, 40.0 MHz or 48.0 MHz. USB_REFCLKIN jitter tolerance is 50 ppm (maximum).

Table 6-84 Switching Characteristics Over Recommended Operating Conditions for USB0 [USB2.0] (see Figure 6-45)

NO.	PARAMETER		1.3V, 1.2V, 1.1V, 1.0V						UNIT
			LOW SPEED 1.5 Mbps		FULL SPEED 12 Mbps		HIGH SPEED 480 Mbps
			MIN	MAX	MIN	MAX	MIN	MAX
1	t_r(D)	Rise time, USB_DP and USB_DM signals⁽¹⁾	75	300	4	20	0.5		ns
2	t_f(D)	Fall time, USB_DP and USB_DM signals⁽¹⁾	75	300	4	20	0.5		ns
3	t_rfM	Rise/Fall time, matching⁽²⁾	80	120	90	111	–	–	%
4	V_CRS	Output signal cross-over voltage⁽¹⁾	1.3	2	1.3	2	–	–	V
5	t_jr(source)NT	Source (Host) Driver jitter, next transition		2		2		⁽⁴⁾	ns
	t_jr(FUNC)NT	Function Driver jitter, next transition		25		2		⁽⁴⁾	ns
6	t_jr(source)PT	Source (Host) Driver jitter, paired transition⁽³⁾		1		1		⁽⁴⁾	ns
	t_jr(FUNC)PT	Function Driver jitter, paired transition		10		1		⁽⁴⁾	ns
7	t_w(EOPT)	Pulse duration, EOP transmitter	1250	1500	160	175	–	–	ns
8	t_w(EOPR)	Pulse duration, EOP receiver	670		82		–		ns
9	t_(DRATE)	Data Rate		1.5		12		480	Mb/s
10	Z_DRV	Driver Output Resistance	–	–	40.5	49.5	40.5	49.5	Ω
11	Z_INP	Receiver Input Impedance	100k		100k		-	-	Ω

(1) Low Speed: C_L = 200 pF, Full Speed: C_L = 50 pF, High Speed: C_L = 50 pF

(2) t_RFM = (t_r/t_f) x 100. [Excluding the first transaction from the Idle state.]

(3) t_jr = t_px(1) - t_px(0)

(4) For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.

Figure 6-45 USB2.0 Integrated Transceiver Interface Timing

6.20 Ethernet Media Access Controller (EMAC)

The Ethernet Media Access Controller (EMAC) provides an efficient interface between device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The EMAC controls the flow of packet data from the device to the PHY. The MDIO module controls PHY configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the device through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to multiplex and control interrupts.

6.20.1 EMAC Peripheral Register Description(s)

Table 6-85 Ethernet Media Access Controller (EMAC) Registers

BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01E2 3000	TXREV	Transmit Revision Register
0x01E2 3004	TXCONTROL	Transmit Control Register
0x01E2 3008	TXTEARDOWN	Transmit Teardown Register
0x01E2 3010	RXREV	Receive Revision Register
0x01E2 3014	RXCONTROL	Receive Control Register
0x01E2 3018	RXTEARDOWN	Receive Teardown Register
0x01E2 3080	TXINTSTATRAW	Transmit Interrupt Status (Unmasked) Register
0x01E2 3084	TXINTSTATMASKED	Transmit Interrupt Status (Masked) Register
0x01E2 3088	TXINTMASKSET	Transmit Interrupt Mask Set Register
0x01E2 308C	TXINTMASKCLEAR	Transmit Interrupt Clear Register
0x01E2 3090	MACINVECTOR	MAC Input Vector Register
0x01E2 3094	MACEOIVECTOR	MAC End Of Interrupt Vector Register
0x01E2 30A0	RXINTSTATRAW	Receive Interrupt Status (Unmasked) Register
0x01E2 30A4	RXINTSTATMASKED	Receive Interrupt Status (Masked) Register
0x01E2 30A8	RXINTMASKSET	Receive Interrupt Mask Set Register
0x01E2 30AC	RXINTMASKCLEAR	Receive Interrupt Mask Clear Register
0x01E2 30B0	MACINTSTATRAW	MAC Interrupt Status (Unmasked) Register
0x01E2 30B4	MACINTSTATMASKED	MAC Interrupt Status (Masked) Register
0x01E2 30B8	MACINTMASKSET	MAC Interrupt Mask Set Register
0x01E2 30BC	MACINTMASKCLEAR	MAC Interrupt Mask Clear Register
0x01E2 3100	RXMBPENABLE	Receive Multicast/Broadcast/Promiscuous Channel Enable Register
0x01E2 3104	RXUNICASTSET	Receive Unicast Enable Set Register
0x01E2 3108	RXUNICASTCLEAR	Receive Unicast Clear Register
0x01E2 310C	RXMAXLEN	Receive Maximum Length Register
0x01E2 3110	RXBUFFEROFFSET	Receive Buffer Offset Register
0x01E2 3114	RXFILTERLOWTHRESH	Receive Filter Low Priority Frame Threshold Register
0x01E2 3120	RX0FLOWTHRESH	Receive Channel 0 Flow Control Threshold Register
0x01E2 3124	RX1FLOWTHRESH	Receive Channel 1 Flow Control Threshold Register
0x01E2 3128	RX2FLOWTHRESH	Receive Channel 2 Flow Control Threshold Register
0x01E2 312C	RX3FLOWTHRESH	Receive Channel 3 Flow Control Threshold Register
0x01E2 3130	RX4FLOWTHRESH	Receive Channel 4 Flow Control Threshold Register
0x01E2 3134	RX5FLOWTHRESH	Receive Channel 5 Flow Control Threshold Register
0x01E2 3138	RX6FLOWTHRESH	Receive Channel 6 Flow Control Threshold Register
0x01E2 313C	RX7FLOWTHRESH	Receive Channel 7 Flow Control Threshold Register
0x01E2 3140	RX0FREEBUFFER	Receive Channel 0 Free Buffer Count Register
0x01E2 3144	RX1FREEBUFFER	Receive Channel 1 Free Buffer Count Register
0x01E2 3148	RX2FREEBUFFER	Receive Channel 2 Free Buffer Count Register
0x01E2 314C	RX3FREEBUFFER	Receive Channel 3 Free Buffer Count Register
0x01E2 3150	RX4FREEBUFFER	Receive Channel 4 Free Buffer Count Register
0x01E2 3154	RX5FREEBUFFER	Receive Channel 5 Free Buffer Count Register
0x01E2 3158	RX6FREEBUFFER	Receive Channel 6 Free Buffer Count Register
0x01E2 315C	RX7FREEBUFFER	Receive Channel 7 Free Buffer Count Register
0x01E2 3160	MACCONTROL	MAC Control Register
0x01E2 3164	MACSTATUS	MAC Status Register
0x01E2 3168	EMCONTROL	Emulation Control Register
0x01E2 316C	FIFOCONTROL	FIFO Control Register
0x01E2 3170	MACCONFIG	MAC Configuration Register
0x01E2 3174	SOFTRESET	Soft Reset Register
0x01E2 31D0	MACSRCADDRLO	MAC Source Address Low Bytes Register
0x01E2 31D4	MACSRCADDRHI	MAC Source Address High Bytes Register
0x01E2 31D8	MACHASH1	MAC Hash Address Register 1
0x01E2 31DC	MACHASH2	MAC Hash Address Register 2
0x01E2 31E0	BOFFTEST	Back Off Test Register
0x01E2 31E4	TPACETEST	Transmit Pacing Algorithm Test Register
0x01E2 31E8	RXPAUSE	Receive Pause Timer Register
0x01E2 31EC	TXPAUSE	Transmit Pause Timer Register
0x01E2 3200 - 0x01E2 32FC	(see Table 6-86)	EMAC Statistics Registers
0x01E2 3500	MACADDRLO	MAC Address Low Bytes Register, Used in Receive Address Matching
0x01E2 3504	MACADDRHI	MAC Address High Bytes Register, Used in Receive Address Matching
0x01E2 3508	MACINDEX	MAC Index Register
0x01E2 3600	TX0HDP	Transmit Channel 0 DMA Head Descriptor Pointer Register
0x01E2 3604	TX1HDP	Transmit Channel 1 DMA Head Descriptor Pointer Register
0x01E2 3608	TX2HDP	Transmit Channel 2 DMA Head Descriptor Pointer Register
0x01E2 360C	TX3HDP	Transmit Channel 3 DMA Head Descriptor Pointer Register
0x01E2 3610	TX4HDP	Transmit Channel 4 DMA Head Descriptor Pointer Register
0x01E2 3614	TX5HDP	Transmit Channel 5 DMA Head Descriptor Pointer Register
0x01E2 3618	TX6HDP	Transmit Channel 6 DMA Head Descriptor Pointer Register
0x01E2 361C	TX7HDP	Transmit Channel 7 DMA Head Descriptor Pointer Register
0x01E2 3620	RX0HDP	Receive Channel 0 DMA Head Descriptor Pointer Register
0x01E2 3624	RX1HDP	Receive Channel 1 DMA Head Descriptor Pointer Register
0x01E2 3628	RX2HDP	Receive Channel 2 DMA Head Descriptor Pointer Register
0x01E2 362C	RX3HDP	Receive Channel 3 DMA Head Descriptor Pointer Register
0x01E2 3630	RX4HDP	Receive Channel 4 DMA Head Descriptor Pointer Register
0x01E2 3634	RX5HDP	Receive Channel 5 DMA Head Descriptor Pointer Register
0x01E2 3638	RX6HDP	Receive Channel 6 DMA Head Descriptor Pointer Register
0x01E2 363C	RX7HDP	Receive Channel 7 DMA Head Descriptor Pointer Register
0x01E2 3640	TX0CP	Transmit Channel 0 Completion Pointer Register
0x01E2 3644	TX1CP	Transmit Channel 1 Completion Pointer Register
0x01E2 3648	TX2CP	Transmit Channel 2 Completion Pointer Register
0x01E2 364C	TX3CP	Transmit Channel 3 Completion Pointer Register
0x01E2 3650	TX4CP	Transmit Channel 4 Completion Pointer Register
0x01E2 3654	TX5CP	Transmit Channel 5 Completion Pointer Register
0x01E2 3658	TX6CP	Transmit Channel 6 Completion Pointer Register
0x01E2 365C	TX7CP	Transmit Channel 7 Completion Pointer Register
0x01E2 3660	RX0CP	Receive Channel 0 Completion Pointer Register
0x01E2 3664	RX1CP	Receive Channel 1 Completion Pointer Register
0x01E2 3668	RX2CP	Receive Channel 2 Completion Pointer Register
0x01E2 366C	RX3CP	Receive Channel 3 Completion Pointer Register
0x01E2 3670	RX4CP	Receive Channel 4 Completion Pointer Register
0x01E2 3674	RX5CP	Receive Channel 5 Completion Pointer Register
0x01E2 3678	RX6CP	Receive Channel 6 Completion Pointer Register
0x01E2 367C	RX7CP	Receive Channel 7 Completion Pointer Register

Table 6-86 EMAC Statistics Registers

BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01E2 3200	RXGOODFRAMES	Good Receive Frames Register
0x01E2 3204	RXBCASTFRAMES	Broadcast Receive Frames Register (Total number of good broadcast frames received)
0x01E2 3208	RXMCASTFRAMES	Multicast Receive Frames Register (Total number of good multicast frames received)
0x01E2 320C	RXPAUSEFRAMES	Pause Receive Frames Register
0x01E2 3210	RXCRCERRORS	Receive CRC Errors Register (Total number of frames received with CRC errors)
0x01E2 3214	RXALIGNCODEERRORS	Receive Alignment/Code Errors Register (Total number of frames received with alignment/code errors)
0x01E2 3218	RXOVERSIZED	Receive Oversized Frames Register (Total number of oversized frames received)
0x01E2 321C	RXJABBER	Receive Jabber Frames Register (Total number of jabber frames received)
0x01E2 3220	RXUNDERSIZED	Receive Undersized Frames Register (Total number of undersized frames received)
0x01E2 3224	RXFRAGMENTS	Receive Frame Fragments Register
0x01E2 3228	RXFILTERED	Filtered Receive Frames Register
0x01E2 322C	RXQOSFILTERED	Received QOS Filtered Frames Register
0x01E2 3230	RXOCTETS	Receive Octet Frames Register (Total number of received bytes in good frames)
0x01E2 3234	TXGOODFRAMES	Good Transmit Frames Register (Total number of good frames transmitted)
0x01E2 3238	TXBCASTFRAMES	Broadcast Transmit Frames Register
0x01E2 323C	TXMCASTFRAMES	Multicast Transmit Frames Register
0x01E2 3240	TXPAUSEFRAMES	Pause Transmit Frames Register
0x01E2 3244	TXDEFERRED	Deferred Transmit Frames Register
0x01E2 3248	TXCOLLISION	Transmit Collision Frames Register
0x01E2 324C	TXSINGLECOLL	Transmit Single Collision Frames Register
0x01E2 3250	TXMULTICOLL	Transmit Multiple Collision Frames Register
0x01E2 3254	TXEXCESSIVECOLL	Transmit Excessive Collision Frames Register
0x01E2 3258	TXLATECOLL	Transmit Late Collision Frames Register
0x01E2 325C	TXUNDERRUN	Transmit Underrun Error Register
0x01E2 3260	TXCARRIERSENSE	Transmit Carrier Sense Errors Register
0x01E2 3264	TXOCTETS	Transmit Octet Frames Register
0x01E2 3268	FRAME64	Transmit and Receive 64 Octet Frames Register
0x01E2 326C	FRAME65T127	Transmit and Receive 65 to 127 Octet Frames Register
0x01E2 3270	FRAME128T255	Transmit and Receive 128 to 255 Octet Frames Register
0x01E2 3274	FRAME256T511	Transmit and Receive 256 to 511 Octet Frames Register
0x01E2 3278	FRAME512T1023	Transmit and Receive 512 to 1023 Octet Frames Register
0x01E2 327C	FRAME1024TUP	Transmit and Receive 1024 to 1518 Octet Frames Register
0x01E2 3280	NETOCTETS	Network Octet Frames Register
0x01E2 3284	RXSOFOVERRUNS	Receive FIFO or DMA Start of Frame Overruns Register
0x01E2 3288	RXMOFOVERRUNS	Receive FIFO or DMA Middle of Frame Overruns Register
0x01E2 328C	RXDMAOVERRUNS	Receive DMA Start of Frame and Middle of Frame Overruns Register

Table 6-87 EMAC Control Module Registers

BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01E2 2000	REV	EMAC Control Module Revision Register
0x01E2 2004	SOFTRESET	EMAC Control Module Software Reset Register
0x01E2 200C	INTCONTROL	EMAC Control Module Interrupt Control Register
0x01E2 2010	C0RXTHRESHEN	EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable Register
0x01E2 2014	C0RXEN	EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register
0x01E2 2018	C0TXEN	EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register
0x01E2 201C	C0MISCEN	EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable Register
0x01E2 2020	C1RXTHRESHEN	EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable Register
0x01E2 2024	C1RXEN	EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register
0x01E2 2028	C1TXEN	EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register
0x01E2 202C	C1MISCEN	EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register
0x01E2 2030	C2RXTHRESHEN	EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register
0x01E2 2034	C2RXEN	EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register
0x01E2 2038	C2TXEN	EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register
0x01E2 203C	C2MISCEN	EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable Register
0x01E2 2040	C0RXTHRESHSTAT	EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status Register
0x01E2 2044	C0RXSTAT	EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register
0x01E2 2048	C0TXSTAT	EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register
0x01E2 204C	C0MISCSTAT	EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status Register
0x01E2 2050	C1RXTHRESHSTAT	EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status Register
0x01E2 2054	C1RXSTAT	EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register
0x01E2 2058	C1TXSTAT	EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register
0x01E2 205C	C1MISCSTAT	EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status Register
0x01E2 2060	C2RXTHRESHSTAT	EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status Register
0x01E2 2064	C2RXSTAT	EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register
0x01E2 2068	C2TXSTAT	EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register
0x01E2 206C	C2MISCSTAT	EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status Register
0x01E2 2070	C0RXIMAX	EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond Register
0x01E2 2074	C0TXIMAX	EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond Register
0x01E2 2078	C1RXIMAX	EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond Register
0x01E2 207C	C1TXIMAX	EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register
0x01E2 2080	C2RXIMAX	EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register
0x01E2 2084	C2TXIMAX	EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register

Table 6-88 EMAC Control Module RAM

BYTE ADDRESS	DESCRIPTION
0x01E2 0000 - 0x01E2 1FFF	EMAC Local Buffer Descriptor Memory

6.20.1.1 EMAC Electrical Data/Timing

Table 6-89 Timing Requirements for MII_RXCLK (see Figure 6-46)

NO.			1.3V, 1.2V, 1.1V				1.0V		UNIT
			10 Mbps		100 Mbps		10 Mbps
			MIN	MAX	MIN	MAX	MIN	MAX
1	t_{c(MII_RXCLK)}	Cycle time, MII_RXCLK	400		40		400		ns
2	t_{w(MII_RXCLKH)}	Pulse duration, MII_RXCLK high	140		14		140		ns
3	t_{w(MII_RXCLKL)}	Pulse duration, MII_RXCLK low	140		14		140		ns

Figure 6-46 MII_RXCLK Timing (EMAC - Receive)

Table 6-90 Timing Requirements for MII_TXCLK (see Figure 6-47)

NO.			1.3V, 1.2V, 1.1V				1.0V		UNIT
			10 Mbps		100 Mbps		10 Mbps
			MIN	MAX	MIN	MAX	MIN	MAX
1	t_{c(MII_TXCLK)}	Cycle time, MII_TXCLK	400		40		400		ns
2	t_{w(MII_TXCLKH)}	Pulse duration, MII_TXCLK high	140		14		140		ns
3	t_{w(MII_TXCLKL)}	Pulse duration, MII_TXCLK low	140		14		140		ns

Figure 6-47 MII_TXCLK Timing (EMAC - Transmit)

Table 6-91 Timing Requirements for EMAC MII Receive 10/100 Mbit/s⁽¹⁾ (see Figure 6-48)

NO.			1.3V, 1.2V, 1.1V, 1.0V		UNIT
NO.			MIN	MAX	UNIT
1	t_{su(MRXD-MII_RXCLKH)}	Setup time, receive selected signals valid before MII_RXCLK high	8		ns
2	t_{h(MII_RXCLKH-MRXD)}	Hold time, receive selected signals valid after MII_RXCLK high	8		ns

(1) Receive selected signals include: MII_RXD[3]-MII_RXD[0], MII_RXDV, and MII_RXER.

Figure 6-48 EMAC Receive Interface Timing

Table 6-92 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s⁽¹⁾ (see Figure 6-49)

NO.	PARAMETER		1.3V, 1.2V, 1.1V		1.0V		UNIT
NO.	PARAMETER		MIN	MAX	MIN	MAX	UNIT
1	t_{d(MII_TXCLKH-MTXD)}	Delay time, MII_TXCLK high to transmit selected signals valid	2	25	2	32	ns

(1) Transmit selected signals include: MTXD3-MTXD0, and MII_TXEN.

Figure 6-49 EMAC Transmit Interface Timing

Table 6-93 Timing Requirements for EMAC RMII

NO.			1.3V, 1.2V, 1.1V⁽¹⁾			UNIT
NO.			MIN	TYP	MAX	UNIT
1	tc(REFCLK)	Cycle Time, RMII_MHZ_50_CLK		20		ns
2	tw(REFCLKH)	Pulse Width, RMII_MHZ_50_CLK High	7		13	ns
3	tw(REFCLKL)	Pulse Width, RMII_MHZ_50_CLK Low	7		13	ns
6	tsu(RXD-REFCLK)	Input Setup Time, RXD Valid before RMII_MHZ_50_CLK High	4			ns
7	th(REFCLK-RXD)	Input Hold Time, RXD Valid after RMII_MHZ_50_CLK High	2			ns
8	tsu(CRSDV-REFCLK)	Input Setup Time, CRSDV Valid before RMII_MHZ_50_CLK High	4			ns
9	th(REFCLK-CRSDV)	Input Hold Time, CRSDV Valid after RMII_MHZ_50_CLK High	2			ns
10	tsu(RXER-REFCLK)	Input Setup Time, RXER Valid before RMII_MHZ_50_CLK High	4			ns
11	th(REFCLKR-RXER)	Input Hold Time, RXER Valid after RMII_MHZ_50_CLK High	2			ns

(1) RMII is not supported at operating points below 1.1V nominal

Note: Per the RMII industry specification, the RMII reference clock (RMII_MHZ_50_CLK) must have jitter tolerance of 50 ppm or less.

Table 6-94 Switching Characteristics Over Recommended Operating Conditions for EMAC RMII

NO.	PARAMETER		1.3V, 1.2V, 1.1V⁽¹⁾			UNIT
NO.	PARAMETER		MIN	TYP	MAX	UNIT
4	td(REFCLK-TXD)	Output Delay Time, RMII_MHZ_50_CLK High to TXD Valid	2.5		13	ns
5	td(REFCLK-TXEN)	Output Delay Time, RMII_MHZ_50_CLK High to TXEN Valid	2.5		13	ns

(1) RMII is not supported at operating points below 1.1V nominal.

Figure 6-50 RMII Timing Diagram

6.21 Management Data Input/Output (MDIO)

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. Only one PHY may be connected at any given time.

6.21.1 MDIO Register Description(s)

Table 6-95 MDIO Register Memory Map

BYTE ADDRESS	ACRONYM	REGISTER NAME
0x01E2 4000	REV	Revision Identification Register
0x01E2 4004	CONTROL	MDIO Control Register
0x01E2 4008	ALIVE	MDIO PHY Alive Status Register
0x01E2 400C	LINK	MDIO PHY Link Status Register
0x01E2 4010	LINKINTRAW	MDIO Link Status Change Interrupt (Unmasked) Register
0x01E2 4014	LINKINTMASKED	MDIO Link Status Change Interrupt (Masked) Register
0x01E2 4018	–	Reserved
0x01E2 4020	USERINTRAW	MDIO User Command Complete Interrupt (Unmasked) Register
0x01E2 4024	USERINTMASKED	MDIO User Command Complete Interrupt (Masked) Register
0x01E2 4028	USERINTMASKSET	MDIO User Command Complete Interrupt Mask Set Register
0x01E2 402C	USERINTMASKCLEAR	MDIO User Command Complete Interrupt Mask Clear Register
0x01E2 4030 - 0x01E2 407C	–	Reserved
0x01E2 4080	USERACCESS0	MDIO User Access Register 0
0x01E2 4084	USERPHYSEL0	MDIO User PHY Select Register 0
0x01E2 4088	USERACCESS1	MDIO User Access Register 1
0x01E2 408C	USERPHYSEL1	MDIO User PHY Select Register 1
0x01E2 4090 - 0x01E2 47FF	–	Reserved

6.21.2 Management Data Input/Output (MDIO) Electrical Data/Timing

Table 6-96 Timing Requirements for MDIO Input (see Figure 6-51 and Figure 6-52)

NO.			1.3V, 1.2V, 1.1V		1.0V		UNIT
NO.			MIN	MAX	MIN	MAX	UNIT
1	t_c(MDCLK)	Cycle time, MDCLK	400		400		ns
2	t_w(MDCLK)	Pulse duration, MDCLK high/low	180		180		ns
3	t_t(MDCLK)	Transition time, MDCLK		5		5	ns
4	t_{su(MDIO-MDCLKH)}	Setup time, MDIO data input valid before MDCLK high	16		21		ns
5	t_{h(MDCLKH-MDIO)}	Hold time, MDIO data input valid after MDCLK high	0		0		ns

Figure 6-51 MDIO Input Timing

Table 6-97 Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 6-52)

NO.	PARAMETER		1.3V, 1.2V, 1.1V, 1.0V		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
7	t_{d(MDCLKL-MDIO)}	Delay time, MDCLK low to MDIO data output valid	0	100	ns

Figure 6-52 MDIO Output Timing

6.22 Host-Port Interface (UHPI)

6.22.1 HPI Device-Specific Information

The device includes a user-configurable 16-bit Host-port interface (HPI16).

The host port interface (UHPI) provides a parallel port interface through which an external host processor can directly access the processor's resources (configuration and program/data memories). The external host device is asynchronous to the CPU clock and functions as a master to the HPI interface. The UHPI enables a host device and the processor to exchange information via internal or external memory. Dedicated address (HPIA) and data (HPID) registers within the UHPI provide the data path between the external host interface and the processor resources. A UHPI control register (HPIC) is available to the host and the CPU for various configuration and interrupt functions.

6.22.2 HPI Peripheral Register Description(s)

Table 6-98 HPI Control Registers

BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION	COMMENTS
0x01E1 0000	PID	Peripheral Identification Register
0x01E1 0004	PWREMU_MGMT	HPI power and emulation management register	The CPU has read/write access to the PWREMU_MGMT register.
0x01E1 0008	-	Reserved
0x01E1 000C	GPIO_EN	General Purpose IO Enable Register
0x01E1 0010	GPIO_DIR1	General Purpose IO Direction Register 1
0x01E1 0014	GPIO_DAT1	General Purpose IO Data Register 1
0x01E1 0018	GPIO_DIR2	General Purpose IO Direction Register 2
0x01E1 001C	GPIO_DAT2	General Purpose IO Data Register 2
0x01E1 0020	GPIO_DIR3	General Purpose IO Direction Register 3
0x01E1 0024	GPIO_DAT3	General Purpose IO Data Register 3
01E1 0028	-	Reserved
01E1 002C	-	Reserved
01E1 0030	HPIC	HPI control register	The Host and the CPU both have read/write access to the HPIC register.
01E1 0034	HPIA (HPIAW)⁽¹⁾	HPI address register (Write)	The Host has read/write access to the HPIA registers. The CPU has only read access to the HPIA registers.
01E1 0038	HPIA (HPIAR)⁽¹⁾	HPI address register (Read)
01E1 000C - 01E1 07FF	-	Reserved

(1) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the perspective of the Host. The CPU can access HPIAW and HPIAR independently.

6.22.3 HPI Electrical Data/Timing

Table 6-99 Timing Requirements for Host-Port Interface [1.2V, 1.1V]⁽¹⁾ ⁽²⁾

NO.			1.3V, 1.2V, 1.1V, 1.0V		UNIT
NO.			MIN	MAX	UNIT
1	t_{su(SELV-HSTBL)}	Setup time, select signals⁽³⁾ valid before UHPI_HSTROBE low	5		ns
2	t_{h(HSTBL-SELV)}	Hold time, select signals⁽³⁾ valid after UHPI_HSTROBE low	2		ns
3	t_w(HSTBL)	Pulse duration, UHPI_HSTROBE active low	15		ns
4	t_w(HSTBH)	Pulse duration, UHPI_HSTROBE inactive high between consecutive accesses	2M		ns
9	t_{su(SELV-HASL)}	Setup time, selects signals valid before UHPI_HAS low	5		ns
10	t_h(HASL-SELV)	Hold time, select signals valid after UHPI_HAS low	2		ns
11	t_{su(HDV-HSTBH)}	Setup time, host data valid before UHPI_HSTROBE high	5		ns
12	t_h(HSTBH-HDV)	Hold time, host data valid after UHPI_HSTROBE high	2		ns
13	t_{h(HRDYL-HSTBH)}	Hold time, UHPI_HSTROBE high after UHPI_HRDY low. UHPI_HSTROBE should not be inactivated until UHPI_HRDY is active (low); otherwise, HPI writes will not complete properly.	2		ns
16	t_{su(HASL-HSTBL)}	Setup time, UHPI_HAS low before UHPI_HSTROBE low	5		ns
17	t_{h(HSTBL-HASH)}	Hold time, UHPI_HAS low after UHPI_HSTROBE low	2		ns

(1) UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.

(2) M=SYSCLK2 period in ns.

(3) Select signals include: HCNTL[1:0], HR/W and HHWIL.

Table 6-100 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.3V, 1.2V, 1.1V]⁽¹⁾ ⁽²⁾ ⁽³⁾

NO.	PARAMETER			1.3V, 1.2V		1.1V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	UNIT
5	t_{d(HSTBL-HRDYV)}	Delay time, HSTROBE low to HRDY valid	For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready): Case 1: Back-to-back HPIA writes (can be either first or second half-word) Case 2: HPIA write following a PREFETCH command (can be either first or second half-word) Case 3: HPID write when FIFO is full or flushing (can be either first or second half-word) Case 4: HPIA write and Write FIFO not empty For HPI Read, HRDY can go high (not ready) for these HPI Read conditions: Case 1: HPID read (with auto-increment) and data not in Read FIFO (can only happen to first half-word of HPID access) Case 2: First half-word access of HPID Read without auto-increment For HPI Read, HRDY stays low (ready) for these HPI Read conditions: Case 1: HPID read with auto-increment and data is already in Read FIFO (applies to either half-word of HPID access) Case 2: HPID read without auto-increment and data is already in Read FIFO (always applies to second half-word of HPID access) Case 3: HPIC or HPIA read (applies to either half-word access)		15		17	ns
5a	t_{d(HASL-HRDYV)}	Delay time, HAS low to HRDY valid			15		17	ns
6	t_{en(HSTBL-HDLZ)}	Enable time, HD driven from HSTROBE low		1.5		1.5		ns
7	t_d(HRDYL-HDV)	Delay time, HRDY low to HD valid			0		0	ns
8	t_{oh(HSTBH-HDV)}	Output hold time, HD valid after HSTROBE high		1.5		1.5		ns
14	t_{dis(HSTBH-HDHZ)}	Disable time, HD high-impedance from HSTROBE high			15		17	ns
15	t_d(HSTBL-HDV)	Delay time, HSTROBE low to HD valid	For HPI Read. Applies to conditions where data is already residing in HPID/FIFO: Case 1: HPIC or HPIA read Case 2: First half-word of HPID read with auto-increment and data is already in Read FIFO Case 3: Second half-word of HPID read with or without auto-increment		15		17	ns
18	t_{d(HSTBH-HRDYV)}	Delay time, HSTROBE high to HRDY valid	For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready): Case 1: HPID write when Write FIFO is full (can happen to either half-word) Case 2: HPIA write (can happen to either half-word) Case 3: HPID write without auto-increment (only happens to second half-word)		15		17	ns

(1) M=SYSCLK2 period in ns.

(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(3) By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).

Table 6-101 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.0V]⁽¹⁾ ⁽²⁾ ⁽³⁾

NO.	PARAMETER			1.0V		UNIT
NO.	PARAMETER			MIN	MAX	UNIT
5	t_{d(HSTBL-HRDYV)}	Delay time, HSTROBE low to HRDY valid	For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready): Case 1: Back-to-back HPIA writes (can be either first or second half-word) Case 2: HPIA write following a PREFETCH command (can be either first or second half-word) Case 3: HPID write when FIFO is full or flushing (can be either first or second half-word) Case 4: HPIA write and Write FIFO not empty For HPI Read, HRDY can go high (not ready) for these HPI Read conditions: Case 1: HPID read (with auto-increment) and data not in Read FIFO (can only happen to first half-word of HPID access) Case 2: First half-word access of HPID Read without auto-increment For HPI Read, HRDY stays low (ready) for these HPI Read conditions: Case 1: HPID read with auto-increment and data is already in Read FIFO (applies to either half-word of HPID access) Case 2: HPID read without auto-increment and data is already in Read FIFO (always applies to second half-word of HPID access) Case 3: HPIC or HPIA read (applies to either half-word access)		22	ns
5a	t_{d(HASL-HRDYV)}	Delay time, HAS low to HRDY valid			22	ns
6	t_{en(HSTBL-HDLZ)}	Enable time, HD driven from HSTROBE low		1.5		ns
7	t_d(HRDYL-HDV)	Delay time, HRDY low to HD valid			0	ns
8	t_{oh(HSTBH-HDV)}	Output hold time, HD valid after HSTROBE high		1.5		ns
14	t_{dis(HSTBH-HDHZ)}	Disable time, HD high-impedance from HSTROBE high			22	ns
15	t_d(HSTBL-HDV)	Delay time, HSTROBE low to HD valid	For HPI Read. Applies to conditions where data is already residing in HPID/FIFO: Case 1: HPIC or HPIA read Case 2: First half-word of HPID read with auto-increment and data is already in Read FIFO Case 3: Second half-word of HPID read with or without auto-increment		22	ns
18	t_{d(HSTBH-HRDYV)}	Delay time, HSTROBE high to HRDY valid	For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready): Case 1: HPID write when Write FIFO is full (can happen to either half-word) Case 2: HPIA write (can happen to either half-word) Case 3: HPID write without auto-increment (only happens to second half-word)		22	ns

(1) M=SYSCLK2 period in ns.

(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(3) By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).

Figure 6-53 UHPI Read Timing (HAS Not Used, Tied High)

A. For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.

B. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.

Figure 6-54 UHPI Read Timing (HAS Used)

Figure 6-55 UHPI Write Timing (HAS Not Used, Tied High)

A. For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.

B. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.

Figure 6-56 UHPI Write Timing (HAS Used)

6.23 Universal Parallel Port (uPP)

The Universal Parallel Port (uPP) peripheral is a multichannel, high-speed parallel interface with dedicated data lines and minimal control signals. It is designed to interface cleanly with high-speed analog-to-digital converters (ADCs) or digital-to-analog converters (DACs) with up to 16-bit data width (per channel). It may also be interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve high-speed digital data transfer. It can operate in receive mode, transmit mode, or duplex mode, in which its individual channels operate in opposite directions.

The uPP peripheral includes an internal DMA controller to maximize throughput and minimize CPU overhead during high-speed data transmission. All uPP transactions use the internal DMA to provide data to or retrieve data from the I/O channels. The DMA controller includes two DMA channels, which typically service separate I/O channels. The uPP peripheral also supports data interleave mode, in which all DMA resources service a single I/O channel. In this mode, only one I/O channel may be used.

The features of the uPP include:

Programmable data width per channel (from 8 to 16 bits inclusive)
Programmable data justification
- Right-justify with zero extend
- Right-justify with sign extend
- Left-justify with zero fill
Supports multiplexing of interleaved data during SDR transmit
Optional frame START signal with programmable polarity
Optional data ENABLE signal with programmable polarity
Optional synchronization WAIT signal with programmable polarity
Single Data Rate (SDR) or Double data Rate (DDR, interleaved) interface
- Supports multiplexing of interleaved data during SDR transmit
- Supports demultiplexing and multiplexing of interleaved data during DDR transfers

For detailed information on the uPP, see the <peripheral guide reference TBD>.

6.23.1 uPP Register Descriptions

Table 6-102 Universal Parallel Port (uPP) Registers

BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01E1 6000	UPPID	uPP Peripheral Identification Register
0x01E1 6004	UPPCR	uPP Peripheral Control Register
0x01E1 6008	UPDLB	uPP Digital Loopback Register
0x01E1 6010	UPCTL	uPP Channel Control Register
0x01E1 6014	UPICR	uPP Interface Configuration Register
0x01E1 6018	UPIVR	uPP Interface Idle Value Register
0x01E1 601C	UPTCR	uPP Threshold Configuration Register
0x01E1 6020	UPISR	uPP Interrupt Raw Status Register
0x01E1 6024	UPIER	uPP Interrupt Enabled Status Register
0x01E1 6028	UPIES	uPP Interrupt Enable Set Register
0x01E1 602C	UPIEC	uPP Interrupt Enable Clear Register
0x01E1 6030	UPEOI	uPP End-of-Interrupt Register
0x01E1 6040	UPID0	uPP DMA Channel I Descriptor 0 Register
0x01E1 6044	UPID1	uPP DMA Channel I Descriptor 1 Register
0x01E1 6048	UPID2	uPP DMA Channel I Descriptor 2 Register
0x01E1 6050	UPIS0	uPP DMA Channel I Status 0 Register
0x01E1 6054	UPIS1	uPP DMA Channel I Status 1 Register
0x01E1 6058	UPIS2	uPP DMA Channel I Status 2 Register
0x01E1 6060	UPQD0	uPP DMA Channel Q Descriptor 0 Register
0x01E1 6064	UPQD1	uPP DMA Channel Q Descriptor 1 Register
0x01E1 6068	UPQD2	uPP DMA Channel Q Descriptor 2 Register
0x01E1 6070	UPQS0	uPP DMA Channel Q Status 0 Register
0x01E1 6074	UPQS1	uPP DMA Channel Q Status 1 Register
0x01E1 6078	UPQS2	uPP DMA Channel Q Status 2 Register

6.23.2 uPP Electrical Data/Timing

Table 6-103 Timing Requirements for uPP (see Figure 6-57, Figure 6-58, Figure 6-59, Figure 6-60)

NO.				1.3V, 1.2V		1.1V		1.0V		UNIT
NO.				MIN	MAX	MIN	MAX	MIN	MAX	UNIT
1	t_c(INCLK)	Cycle time, CHn_CLK	SDR mode	13.33		20		26.66		ns
1	t_c(INCLK)	Cycle time, CHn_CLK	DDR mode	26.66		40		53.33		ns
2	t_w(INCLKH)	Pulse width, CHn_CLK high	SDR mode	5		8		10		ns
2	t_w(INCLKH)	Pulse width, CHn_CLK high	DDR mode	10		16		20		ns
3	t_w(INCLKL)	Pulse width, CHn_CLK low	SDR mode	5		8		10		ns
3	t_w(INCLKL)	Pulse width, CHn_CLK low	DDR mode	10		16		20		ns
4	t_{su(STV-INCLKH)}	Setup time, CHn_START valid before CHn_CLK high		4		5.5		6.5		ns
5	t_{h(INCLKH-STV)}	Hold time, CHn_START valid after CHn_CLK high		0.8		0.8		0.8		ns
6	t_{su(ENV-INCLKH)}	Setup time, CHn_ENABLE valid before CHn_CLK high		4		5.5		6.5		ns
7	t_{h(INCLKH-ENV)}	Hold time, CHn_ENABLE valid after CHn_CLK high		0.8		0.8		0.8		ns
8	t_{su(DV-INCLKH)}	Setup time, CHn_DATA/XDATA valid before CHn_CLK high		4		5.5		6.5		ns
9	t_h(INCLKH-DV)	Hold time, CHn_DATA/XDATA valid after CHn_CLK high		0.8		0.8		0.8		ns
10	t_{su(DV-INCLKL)}	Setup time, CHn_DATA/XDATA valid before CHn_CLK low		4		5.5		6.5		ns
11	t_h(INCLKL-DV)	Hold time, CHn_DATA/XDATA valid after CHn_CLK low		0.8		0.8		0.8		ns
19	t_{su(WTV-INCLKL)}	Setup time, CHn_WAIT valid before CHn_CLK high		10		12		14		ns
20	t_{h(INCLKL-WTV)}	Hold time, CHn_WAIT valid after CHn_CLK high		0.8		0.8		0.8		ns
21	t_c(2xTXCLK)	Cycle time, 2xTXCLK input clock⁽¹⁾		6.66		10		13.33		ns

(1) 2xTXCLK is an alternate transmit clock source that must be at least 2 times the required uPP transmit clock rate (as it is is divided down by 2 inside the uPP). 2xTXCLK has no specified skew relationship to the CHn_CLOCK and therefore is not shown in the timing diagram.

Table 6-104 Switching Characteristics Over Recommended Operating Conditions for uPP

NO.	PARAMETER			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
12	t_c(OUTCLK)	Cycle time, CHn_CLK	SDR mode	13.33		20		26.66		ns
12	t_c(OUTCLK)	Cycle time, CHn_CLK	DDR mode	26.66		40		53.33		ns
13	t_w(OUTCLKH)	Pulse width, CHn_CLK high	SDR mode	5		8		10		ns
13	t_w(OUTCLKH)	Pulse width, CHn_CLK high	DDR mode	10		16		20		ns
14	t_w(OUTCLKL)	Pulse width, CHn_CLK low	SDR mode	5		8		10		ns
14	t_w(OUTCLKL)	Pulse width, CHn_CLK low	DDR mode	10		16		20		ns
15	t_{d(OUTCLKH-STV)}	Delay time, CHn_START valid after CHn_CLK high		2	11	2	15	2	21	ns
16	t_{d(OUTCLKH-ENV)}	Delay time, CHn_ENABLE valid after CHn_CLK high		2	11	2	15	2	21	ns
17	t_{d(OUTCLKH-DV)}	Delay time, CHn_DATA/XDATA valid after CHn_CLK high		2	11	2	15	2	21	ns
18	t_{d(OUTCLKL-DV)}	Delay time, CHn_DATA/XDATA valid after CHn_CLK low		2	11	2	15	2	21	ns

TMS320C6746 upp_freon_timing1_prs586.gif

Figure 6-57 uPP Single Data Rate (SDR) Receive Timing

TMS320C6746 upp_freon_timing2_prs586.gif

Figure 6-58 uPP Double Data Rate (DDR) Receive Timing

TMS320C6746 upp_freon_timing3_prs586.gif

Figure 6-59 uPP Single Data Rate (SDR) Transmit Timing

TMS320C6746 upp_freon_timing4_prs586.gif

Figure 6-60 uPP Double Data Rate (DDR) Transmit Timing

6.24 Video Port Interface (VPIF)

The Video Port Interface (VPIF) allows the capture and display of digital video streams. Features include:

Up to 2 Video Capture Channels (Channel 0 and Channel 1)
- Two 8-bit Standard-Definition (SD) Video with embedded timing codes (BT.656)
- Single 16-bit High-Definition (HD) Video with embedded timing codes (BT.1120)
- Single Raw Video (8-/10-/12-bit)
Up to 2 Video Display Channels (Channel 2 and Channel 3)
- Two 8-bit SD Video Display with embedded timing codes (BT.656)
- Single 16-bit HD Video Display with embedded timing codes (BT.1120)

The VPIF capture channel input data format is selectable based on the settings of the specific Channel Control Register (Channels 0–3). The VPIF Raw Video data-bus width is selectable based on the settings of the Channel 0 Control Register.

6.24.1 VPIF Register Descriptions

Table 6-105 shows the VPIF registers.

Table 6-105 Video Port Interface (VPIF) Registers

BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01E1 7000	PID	Peripheral identification register
0x01E1 7004	CH0_CTRL	Channel 0 control register
0x01E1 7008	CH1_CTRL	Channel 1 control register
0x01E1 700C	CH2_CTRL	Channel 2 control register
0x01E1 7010	CH3_CTRL	Channel 3 control register
0x01E1 7014 - 0x01E1 701F	-	Reserved
0x01E1 7020	INTEN	Interrupt enable
0x01E1 7024	INTENSET	Interrupt enable set
0x01E1 7028	INTENCLR	Interrupt enable clear
0x01E1 702C	INTSTAT	Interrupt status
0x01E1 7030	INTSTATCLR	Interrupt status clear
0x01E1 7034	EMU_CTRL	Emulation control
0x01E1 7038	DMA_SIZE	DMA size control
0x01E1 703C - 0x01E1 703F	-	Reserved
CAPTURE CHANNEL 0 REGISTERS
0x01E1 7040	CH0_TY_STRTADR	Channel 0 Top Field luma buffer start address
0x01E1 7044	CH0_BY_STRTADR	Channel 0 Bottom Field luma buffer start address
0x01E1 7048	CH0_TC_STRTADR	Channel 0 Top Field chroma buffer start address
0x01E1 704C	CH0_BC_STRTADR	Channel 0 Bottom Field chroma buffer start address
0x01E1 7050	CH0_THA_STRTADR	Channel 0 Top Field horizontal ancillary data buffer start address
0x01E1 7054	CH0_BHA_STRTADR	Channel 0 Bottom Field horizontal ancillary data buffer start address
0x01E1 7058	CH0_TVA_STRTADR	Channel 0 Top Field vertical ancillary data buffer start address
0x01E1 705C	CH0_BVA_STRTADR	Channel 0 Bottom Field vertical ancillary data buffer start address
0x01E1 7060	CH0_SUBPIC_CFG	Channel 0 sub-picture configuration
0x01E1 7064	CH0_IMG_ADD_OFST	Channel 0 image data address offset
0x01E1 7068	CH0_HA_ADD_OFST	Channel 0 horizontal ancillary data address offset
0x01E1 706C	CH0_HSIZE_CFG	Channel 0 horizontal data size configuration
0x01E1 7070	CH0_VSIZE_CFG0	Channel 0 vertical data size configuration (0)
0x01E1 7074	CH0_VSIZE_CFG1	Channel 0 vertical data size configuration (1)
0x01E1 7078	CH0_VSIZE_CFG2	Channel 0 vertical data size configuration (2)
0x01E1 707C	CH0_VSIZE	Channel 0 vertical image size
CAPTURE CHANNEL 1 REGISTERS
0x01E1 7080	CH1_TY_STRTADR	Channel 1 Top Field luma buffer start address
0x01E1 7084	CH1_BY_STRTADR	Channel 1 Bottom Field luma buffer start address
0x01E1 7088	CH1_TC_STRTADR	Channel 1 Top Field chroma buffer start address
0x01E1 708C	CH1_BC_STRTADR	Channel 1 Bottom Field chroma buffer start address
0x01E1 7090	CH1_THA_STRTADR	Channel 1 Top Field horizontal ancillary data buffer start address
0x01E1 7094	CH1_BHA_STRTADR	Channel 1 Bottom Field horizontal ancillary data buffer start address
0x01E1 7098	CH1_TVA_STRTADR	Channel 1 Top Field vertical ancillary data buffer start address
0x01E1 709C	CH1_BVA_STRTADR	Channel 1 Bottom Field vertical ancillary data buffer start address
0x01E1 70A0	CH1_SUBPIC_CFG	Channel 1 sub-picture configuration
0x01E1 70A4	CH1_IMG_ADD_OFST	Channel 1 image data address offset
0x01E1 70A8	CH1_HA_ADD_OFST	Channel 1 horizontal ancillary data address offset
0x01E1 70AC	CH1_HSIZE_CFG	Channel 1 horizontal data size configuration
0x01E1 70B0	CH1_VSIZE_CFG0	Channel 1 vertical data size configuration (0)
0x01E1 70B4	CH1_VSIZE_CFG1	Channel 1 vertical data size configuration (1)
0x01E1 70B8	CH1_VSIZE_CFG2	Channel 1 vertical data size configuration (2)
0x01E1 70BC	CH1_VSIZE	Channel 1 vertical image size
DISPLAY CHANNEL 2 REGISTERS
0x01E1 70C0	CH2_TY_STRTADR	Channel 2 Top Field luma buffer start address
0x01E1 70C4	CH2_BY_STRTADR	Channel 2 Bottom Field luma buffer start address
0x01E1 70C8	CH2_TC_STRTADR	Channel 2 Top Field chroma buffer start address
0x01E1 70CC	CH2_BC_STRTADR	Channel 2 Bottom Field chroma buffer start address
0x01E1 70D0	CH2_THA_STRTADR	Channel 2 Top Field horizontal ancillary data buffer start address
0x01E1 70D4	CH2_BHA_STRTADR	Channel 2 Bottom Field horizontal ancillary data buffer start address
0x01E1 70D8	CH2_TVA_STRTADR	Channel 2 Top Field vertical ancillary data buffer start address
0x01E1 70DC	CH2_BVA_STRTADR	Channel 2 Bottom Field vertical ancillary data buffer start address
0x01E1 70E0	CH2_SUBPIC_CFG	Channel 2 sub-picture configuration
0x01E1 70E4	CH2_IMG_ADD_OFST	Channel 2 image data address offset
0x01E1 70E8	CH2_HA_ADD_OFST	Channel 2 horizontal ancillary data address offset
0x01E1 70EC	CH2_HSIZE_CFG	Channel 2 horizontal data size configuration
0x01E1 70F0	CH2_VSIZE_CFG0	Channel 2 vertical data size configuration (0)
0x01E1 70F4	CH2_VSIZE_CFG1	Channel 2 vertical data size configuration (1)
0x01E1 70F8	CH2_VSIZE_CFG2	Channel 2 vertical data size configuration (2)
0x01E1 70FC	CH2_VSIZE	Channel 2 vertical image size
0x01E1 7100	CH2_THA_STRTPOS	Channel 2 Top Field horizontal ancillary data insertion start position
0x01E1 7104	CH2_THA_SIZE	Channel 2 Top Field horizontal ancillary data size
0x01E1 7108	CH2_BHA_STRTPOS	Channel 2 Bottom Field horizontal ancillary data insertion start position
0x01E1 710C	CH2_BHA_SIZE	Channel 2 Bottom Field horizontal ancillary data size
0x01E1 7110	CH2_TVA_STRTPOS	Channel 2 Top Field vertical ancillary data insertion start position
0x01E1 7114	CH2_TVA_SIZE	Channel 2 Top Field vertical ancillary data size
0x01E1 7118	CH2_BVA_STRTPOS	Channel 2 Bottom Field vertical ancillary data insertion start position
0x01E1 711C	CH2_BVA_SIZE	Channel 2 Bottom Field vertical ancillary data size
0x01E1 7120 - 0x01E1 713F	-	Reserved
DISPLAY CHANNEL 3 REGISTERS
0x01E1 7140	CH3_TY_STRTADR	Channel 3 Field 0 luma buffer start address
0x01E1 7144	CH3_BY_STRTADR	Channel 3 Field 1 luma buffer start address
0x01E1 7148	CH3_TC_STRTADR	Channel 3 Field 0 chroma buffer start address
0x01E1 714C	CH3_BC_STRTADR	Channel 3 Field 1 chroma buffer start address
0x01E1 7150	CH3_THA_STRTADR	Channel 3 Field 0 horizontal ancillary data buffer start address
0x01E1 7154	CH3_BHA_STRTADR	Channel 3 Field 1 horizontal ancillary data buffer start address
0x01E1 7158	CH3_TVA_STRTADR	Channel 3 Field 0 vertical ancillary data buffer start address
0x01E1 715C	CH3_BVA_STRTADR	Channel 3 Field 1 vertical ancillary data buffer start address
0x01E1 7160	CH3_SUBPIC_CFG	Channel 3 sub-picture configuration
0x01E1 7164	CH3_IMG_ADD_OFST	Channel 3 image data address offset
0x01E1 7168	CH3_HA_ADD_OFST	Channel 3 horizontal ancillary data address offset
0x01E1 716C	CH3_HSIZE_CFG	Channel 3 horizontal data size configuration
0x01E1 7170	CH3_VSIZE_CFG0	Channel 3 vertical data size configuration (0)
0x01E1 7174	CH3_VSIZE_CFG1	Channel 3 vertical data size configuration (1)
0x01E1 7178	CH3_VSIZE_CFG2	Channel 3 vertical data size configuration (2)
0x01E1 717C	CH3_VSIZE	Channel 3 vertical image size
0x01E1 7180	CH3_THA_STRTPOS	Channel 3 Top Field horizontal ancillary data insertion start position
0x01E1 7184	CH3_THA_SIZE	Channel 3 Top Field horizontal ancillary data size
0x01E1 7188	CH3_BHA_STRTPOS	Channel 3 Bottom Field horizontal ancillary data insertion start position
0x01E1 718C	CH3_BHA_SIZE	Channel 3 Bottom Field horizontal ancillary data size
0x01E1 7190	CH3_TVA_STRTPOS	Channel 3 Top Field vertical ancillary data insertion start position
0x01E1 7194	CH3_TVA_SIZE	Channel 3 Top Field vertical ancillary data size
0x01E1 7198	CH3_BVA_STRTPOS	Channel 3 Bottom Field vertical ancillary data insertion start position
0x01E1 719C	CH3_BVA_SIZE	Channel 3 Bottom Field vertical ancillary data size
0x01E1 71A0 - 0x01E1 71FF	-	Reserved

6.24.2 VPIF Electrical Data/Timing

Table 6-106 Timing Requirements for VPIF VP_CLKINx Inputs⁽¹⁾ (see Figure 6-61)

NO.			1.3V, 1.2V		1.1V		1.0V		UNIT
NO.			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
1	t_c(VKI)	Cycle time, VP_CLKIN0	13.3		20		37		ns
1	t_c(VKI)	Cycle time, VP_CLKIN1/2/3	13.3		20		37		ns
2	t_w(VKIH)	Pulse duration, VP_CLKINx high	0.4C		0.4C		0.4C		ns
3	t_w(VKIL)	Pulse duration, VP_CLKINx low	0.4C		0.4C		0.4C		ns
4	t_t(VKI)	Transition time, VP_CLKINx		5		5		5	ns

(1) C = VP_CLKINx period in ns.

Figure 6-61 Video Port Capture VP_CLKINx Timing

Table 6-107 Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs
(see Figure 6-62)

NO.			1.3V		1.2V		1.1V		1.0V		UNIT
NO.			MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX	UNIT
1	t_{su(VDINV-VKIH)}	Setup time, VP_DINx valid before VP_OSCIN0/1 high	4		4		6		7		ns
2	t_{h(VKIH-VDINV)}	Hold time, VP_DINx valid after VP_CLKIN0/1 high	0.5		0		0		0		ns

Figure 6-62 VPIF Channels 0/1 Video Capture Data and Control Input Timing

Table 6-108 Switching Characteristics Over Recommended Operating Conditions for Video Data Shown With Respect to VP_CLKOUT2/3⁽¹⁾
(see Figure 6-63)

NO.	PARAMETER		1.3V, 1.2V		1.1V		1.0V		UNIT
NO.	PARAMETER		MIN	MAX	MIN	MAX	MIN	MAX	UNIT
1	t_c(VKO)	Cycle time, VP_CLKOUT2/3	13.3		20		37		ns
2	t_w(VKOH)	Pulse duration, VP_CLKOUT2/3 high	0.4C		0.4C		0.4C		ns
3	t_w(VKOL)	Pulse duration, VP_CLKOUT2/3 low	0.4C		0.4C		0.4C		ns
4	t_t(VKO)	Transition time, VP_CLKOUT2/3		5		5		5	ns
11	t_{d(VKOH-VPDOUTV)}	Delay time, VP_CLKOUT2/3 high to VP_DOUTx valid		8.5		12		17	ns
12	t_{d(VCLKOH-VPDOUTIV)}	Delay time, VP_CLKOUT2/3 high to VP_DOUTx invalid	1.5		1.5		1.5		ns

(1) C = VP_CLKO2/3 period in ns.

Figure 6-63 VPIF Channels 2/3 Video Display Data Output Timing With Respect to VP_CLKOUT2/3

6.25 Enhanced Capture (eCAP) Peripheral

The device contains up to three enhanced capture (eCAP) modules. Figure 6-64 shows a functional block diagram of a module.

Uses for ECAP include:

Speed measurements of rotating machinery (e.g. toothed sprockets sensed via Hall sensors)
Elapsed time measurements between position sensor triggers
Period and duty cycle measurements of pulse train signals
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors

The ECAP module described in this specification includes the following features:

32 bit time base
4 event time-stamp registers (each 32 bits)
Edge polarity selection for up to 4 sequenced time-stamp capture events
Interrupt on either of the 4 events
Single shot capture of up to 4 event time-stamps
Continuous mode capture of time-stamps in a 4 deep circular buffer
Absolute time-stamp capture
Difference mode time-stamp capture
All the above resources are dedicated to a single input pin

The eCAP modules are clocked at the ASYNC3 clock domain rate.

Figure 6-64 eCAP Functional Block Diagram

Table 6-109 is the list of the ECAP registers.

Table 6-109 ECAPx Configuration Registers

ECAP0 BYTE ADDRESS	ECAP1 BYTE ADDRESS	ECAP2 BYTE ADDRESS	ACRONYM	DESCRIPTION
0x01F0 6000	0x01F0 7000	0x01F0 8000	TSCTR	Time-Stamp Counter
0x01F0 6004	0x01F0 7004	0x01F0 8004	CTRPHS	Counter Phase Offset Value Register
0x01F0 6008	0x01F0 7008	0x01F0 8008	CAP1	Capture 1 Register
0x01F0 600C	0x01F0 700C	0x01F0 800C	CAP2	Capture 2 Register
0x01F0 6010	0x01F0 7010	0x01F0 8010	CAP3	Capture 3 Register
0x01F0 6014	0x01F0 7014	0x01F0 8014	CAP4	Capture 4 Register
0x01F0 6028	0x01F0 7028	0x01F0 8028	ECCTL1	Capture Control Register 1
0x01F0 602A	0x01F0 702A	0x01F0 802A	ECCTL2	Capture Control Register 2
0x01F0 602C	0x01F0 702C	0x01F0 802C	ECEINT	Capture Interrupt Enable Register
0x01F0 602E	0x01F0 702E	0x01F0 802E	ECFLG	Capture Interrupt Flag Register
0x01F0 6030	0x01F0 7030	0x01F0 8030	ECCLR	Capture Interrupt Clear Register
0x01F0 6032	0x01F0 7032	0x01F0 8032	ECFRC	Capture Interrupt Force Register
0x01F0 605C	0x01F0 705C	0x01F0 805C	REVID	Revision ID

Table 6-110 shows the eCAP timing requirement and Table 6-111 shows the eCAP switching characteristics.

Table 6-110 Timing Requirements for Enhanced Capture (eCAP)

		TEST CONDITIONS	1.3V, 1.2V, 1.1V, 1.0V		UNIT
		TEST CONDITIONS	MIN	MAX	UNIT
t_w(CAP)	Capture input pulse width	Asynchronous	2t_c(SCO)		cycles
t_w(CAP)	Capture input pulse width	Synchronous	2t_c(SCO)		cycles

Table 6-111 Switching Characteristics Over Recommended Operating Conditions for eCAP

PARAMETER		1.3V, 1.2V		1.1V		1.0V		UNIT
PARAMETER		MIN	MAX	MIN	MAX	MIN	MAX	UNIT
t_w(APWM)	Pulse duration, APWMx output high/low	20		20		20		ns

6.26 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)

The device contains two enhanced PWM Modules (eHRPWM). Figure 6-65 shows a block diagram of multiple eHRPWM modules. Figure 6-65 shows the signal interconnections with the eHRPWM.

Figure 6-65 Multiple PWM Modules in a C6746 System

Figure 6-66 eHRPWM Sub-Modules Showing Critical Internal Signal Interconnections

Table 6-112 eHRPWM Module Control and Status Registers Grouped by Submodule

eHRPWM0 BYTE ADDRESS	eHRPWM1 BYTE ADDRESS	ACRONYM	SHADOW	REGISTER DESCRIPTION
Time-Base Submodule Registers
0x01F0 0000	0x01F0 2000	TBCTL	No	Time-Base Control Register
0x01F0 0002	0x01F0 2002	TBSTS	No	Time-Base Status Register
0x01F0 0004	0x01F0 2004	TBPHSHR	No	Extension for HRPWM Phase Register⁽¹⁾
0x01F0 0006	0x01F0 2006	TBPHS	No	Time-Base Phase Register
0x01F0 0008	0x01F0 2008	TBCNT	No	Time-Base Counter Register
0x01F0 000A	0x01F0 200A	TBPRD	Yes	Time-Base Period Register
Counter-Compare Submodule Registers
0x01F0 000E	0x01F0 200E	CMPCTL	No	Counter-Compare Control Register
0x01F0 0010	0x01F0 2010	CMPAHR	No	Extension for HRPWM Counter-Compare A Register⁽¹⁾
0x01F0 0012	0x01F0 2012	CMPA	Yes	Counter-Compare A Register
0x01F0 0014	0x01F0 2014	CMPB	Yes	Counter-Compare B Register
Action-Qualifier Submodule Registers
0x01F0 0016	0x01F0 2016	AQCTLA	No	Action-Qualifier Control Register for Output A (eHRPWMxA)
0x01F0 0018	0x01F0 2018	AQCTLB	No	Action-Qualifier Control Register for Output B (eHRPWMxB)
0x01F0 001A	0x01F0 201A	AQSFRC	No	Action-Qualifier Software Force Register
0x01F0 001C	0x01F0 201C	AQCSFRC	Yes	Action-Qualifier Continuous S/W Force Register Set
Dead-Band Generator Submodule Registers
0x01F0 001E	0x01F0 201E	DBCTL	No	Dead-Band Generator Control Register
0x01F0 0020	0x01F0 2020	DBRED	No	Dead-Band Generator Rising Edge Delay Count Register
0x01F0 0022	0x01F0 2022	DBFED	No	Dead-Band Generator Falling Edge Delay Count Register
PWM-Chopper Submodule Registers
0x01F0 003C	0x01F0 203C	PCCTL	No	PWM-Chopper Control Register
Trip-Zone Submodule Registers
0x01F0 0024	0x01F0 2024	TZSEL	No	Trip-Zone Select Register
0x01F0 0028	0x01F0 2028	TZCTL	No	Trip-Zone Control Register
0x01F0 002A	0x01F0 202A	TZEINT	No	Trip-Zone Enable Interrupt Register
0x01F0 002C	0x01F0 202C	TZFLG	No	Trip-Zone Flag Register
0x01F0 002E	0x01F0 202E	TZCLR	No	Trip-Zone Clear Register
0x01F0 0030	0x01F0 2030	TZFRC	No	Trip-Zone Force Register
Event-Trigger Submodule Registers
0x01F0 0032	0x01F0 2032	ETSEL	No	Event-Trigger Selection Register
0x01F0 0034	0x01F0 2034	ETPS	No	Event-Trigger Pre-Scale Register
0x01F0 0036	0x01F0 2036	ETFLG	No	Event-Trigger Flag Register
0x01F0 0038	0x01F0 2038	ETCLR	No	Event-Trigger Clear Register
0x01F0 003A	0x01F0 203A	ETFRC	No	Event-Trigger Force Register
High-Resolution PWM (HRPWM) Submodule Registers
0x01F0 1040	0x01F0 3040	HRCNFG	No	HRPWM Configuration Register ⁽¹⁾

(1) These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these locations are reserved.

6.26.1 Enhanced Pulse Width Modulator (eHRPWM) Timing

PWM refers to PWM outputs on eHRPWM1-6. Table 6-113 shows the PWM timing requirements and Table 6-114, switching characteristics.

Table 6-113 Timing Requirements for eHRPWM

		TEST CONDITIONS	1.3V, 1.2V, 1.1V, 1.0V		UNIT
		TEST CONDITIONS	MIN	MAX	UNIT
t_w(SYNCIN)	Sync input pulse width	Asynchronous	2t_c(SCO)		cycles
t_w(SYNCIN)	Sync input pulse width	Synchronous	2t_c(SCO)		cycles

Table 6-114 Switching Characteristics Over Recommended Operating Conditions for eHRPWM

PARAMETER		TEST CONDITIONS	1.3V, 1.2V		1.1V		1.0V		UNIT
PARAMETER		TEST CONDITIONS	MIN	MAX	MIN	MAX	MIN	MAX	UNIT
t_w(PWM)	Pulse duration, PWMx output high/low		20		20		26.6		ns
t_w(SYNCOUT)	Sync output pulse width		8t_c(SCO)		8t_c(SCO)		8t_c(SCO)		cycles
t_d(PWM)TZA	Delay time, trip input active to PWM forced high Delay time, trip input active to PWM forced low	no pin load; no additional programmable delay		25		25		25	ns
t_d(TZ-PWM)HZ	Delay time, trip input active to PWM Hi-Z	no additional programmable delay		20		20		20	ns

6.26.2 Trip-Zone Input Timing

A. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.

Figure 6-67 PWM Hi-Z Characteristics

Table 6-115 Trip-Zone input Timing Requirements

		TEST CONDITIONS	1.3V, 1.2V, 1.1V, 1.0V		UNIT
		TEST CONDITIONS	MIN	MAX	UNIT
t_w(TZ)	Pulse duration, TZx input low	Asynchronous	1t_c(SCO)		cycles
t_w(TZ)	Pulse duration, TZx input low	Synchronous	2t_c(SCO)		cycles

6.27 Timers

The timers support the following features:

Configurable as single 64-bit timer or two 32-bit timers
Period timeouts generate interrupts, DMA events or external pin events
8 32-bit compare registers
Compare matches generate interrupt events
Capture capability
64-bit Watchdog capability (Timer64P1 only)

Table 6-116 lists the timer registers.

Table 6-116 Timer Registers

TIMER64P 0 BYTE ADDRESS	TIMER64P 1 BYTE ADDRESS	TIMER64P 2 BYTE ADDRESS	TIMER64P 3 BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01C2 0000	0x01C2 1000	0x01F0 C000	0x01F0 D000	REV	Revision Register
0x01C2 0004	0x01C2 1004	0x01F0 C004	0x01F0 D004	EMUMGT	Emulation Management Register
0x01C2 0008	0x01C2 1008	0x01F0 C008	0x01F0 D008	GPINTGPEN	GPIO Interrupt and GPIO Enable Register
0x01C2 000C	0x01C2 100C	0x01F0 C00C	0x01F0 D00C	GPDATGPDIR	GPIO Data and GPIO Direction Register
0x01C2 0010	0x01C2 1010	0x01F0 C010	0x01F0 D010	TIM12	Timer Counter Register 12
0x01C2 0014	0x01C2 1014	0x01F0 C014	0x01F0 D014	TIM34	Timer Counter Register 34
0x01C2 0018	0x01C2 1018	0x01F0 C018	0x01F0 D018	PRD12	Timer Period Register 12
0x01C2 001C	0x01C2 101C	0x01F0 C01C	0x01F0 D01C	PRD34	Timer Period Register 34
0x01C2 0020	0x01C2 1020	0x01F0 C020	0x01F0 D020	TCR	Timer Control Register
0x01C2 0024	0x01C2 1024	0x01F0 C024	0x01F0 D024	TGCR	Timer Global Control Register
0x01C2 0028	0x01C2 1028	0x01F0 C028	0x01F0 D028	WDTCR	Watchdog Timer Control Register
0x01C2 0034	0x01C2 1034	0x01F0 C034	0x01F0 D034	REL12	Timer Reload Register 12
0x01C2 0038	0x01C2 1038	0x01F0 C038	0x01F0 D038	REL34	Timer Reload Register 34
0x01C2 003C	0x01C2 103C	0x01F0 C03C	0x01F0 D03C	CAP12	Timer Capture Register 12
0x01C2 0040	0x01C2 1040	0x01F0 C040	0x01F0 D040	CAP34	Timer Capture Register 34
0x01C2 0044	0x01C2 1044	0x01F0 C044	0x01F0 D044	INTCTLSTAT	Timer Interrupt Control and Status Register
0x01C2 0060	0x01C2 1060	0x01F0 C060	0x01F0 D060	CMP0	Compare Register 0
0x01C2 0064	0x01C2 1064	0x01F0 C064	0x01F0 D064	CMP1	Compare Register 1
0x01C2 0068	0x01C2 1068	0x01F0 C068	0x01F0 D068	CMP2	Compare Register 2
0x01C2 006C	0x01C2 106C	0x01F0 C06C	0x01F0 D06C	CMP3	Compare Register 3
0x01C2 0070	0x01C2 1070	0x01F0 C070	0x01F0 D070	CMP4	Compare Register 4
0x01C2 0074	0x01C2 1074	0x01F0 C074	0x01F0 D074	CMP5	Compare Register 5
0x01C2 0078	0x01C2 1078	0x01F0 C078	0x01F0 D078	CMP6	Compare Register 6
0x01C2 007C	0x01C2 107C	0x01F0 C07C	0x01F0 D07C	CMP7	Compare Register 7

6.27.1 Timer Electrical Data/Timing

Table 6-117 Timing Requirements for Timer Input⁽¹⁾ ⁽²⁾ (see Figure 6-68)

NO.			1.3V, 1.2V, 1.1V, 1.0V		UNIT
NO.			MIN	MAX	UNIT
1	t_{c(TM64Px_IN12)}	Cycle time, TM64Px_IN12	4P		ns
2	t_w(TINPH)	Pulse duration, TM64Px_IN12 high	0.45C	0.55C	ns
3	t_w(TINPL)	Pulse duration, TM64Px_IN12 low	0.45C	0.55C	ns
4	t_{t(TM64Px_IN12)}	Transition time, TM64Px_IN12		0.25P or 10 ⁽³⁾	ns

(1) P = OSCIN cycle time in ns.

(2) C = TM64P0_IN12 cycle time in ns.

(3) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input signals.

Figure 6-68 Timer Timing

Table 6-118 Switching Characteristics Over Recommended Operating Conditions for Timer Output ⁽¹⁾

NO.	PARAMETER		1.3V, 1.2V, 1.1V, 1.0V		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
5	t_w(TOUTH)	Pulse duration, TM64P0_OUT12 high	4P		ns
6	t_w(TOUTL)	Pulse duration, TM64P0_OUT12 low	4P		ns

(1) P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns.

Figure 6-69 Timer Timing

6.28 Real Time Clock (RTC)

The RTC provides a time reference to an application running on the device. The current date and time is tracked in a set of counter registers that update once per second. The time can be represented in 12-hour or 24-hour mode. The calendar and time registers are buffered during reads and writes so that updates do not interfere with the accuracy of the time and date.

Alarms are available to interrupt the CPU at a particular time, or at periodic time intervals, such as once per minute or once per day. In addition, the RTC can interrupt the CPU every time the calendar and time registers are updated, or at programmable periodic intervals.

The real-time clock (RTC) provides the following features:

100-year calendar (xx00 to xx99)
Counts seconds, minutes, hours, day of the week, date, month, and year with leap year compensation
Binary-coded-decimal (BCD) representation of time, calendar, and alarm
12-hour clock mode (with AM and PM) or 24-hour clock mode
Alarm interrupt
Periodic interrupt
Single interrupt to the CPU
Supports external 32.768-kHz crystal or external clock source of the same frequency
Separate isolated power supply

Figure 6-70 shows a block diagram of the RTC.

Figure 6-70 Real-Time Clock Block Diagram

6.28.1 Clock Source

The clock reference for the RTC is an external 32.768-kHz crystal or an external clock source of the same frequency. The RTC also has a separate power supply that is isolated from the rest of the system. When the CPU and other peripherals are without power, the RTC can remain powered to preserve the current time and calendar information. Even if the RTC is not used, it must remain powered when the rest of the device is powered.

The source for the RTC reference clock may be provided by a crystal or by an external clock source. The RTC has an internal oscillator buffer to support direct operation with a crystal. The crystal is connected between pins RTC_XI and RTC_XO. RTC_XI is the input to the on-chip oscillator and RTC_XO is the output from the oscillator back to the crystal.

An external 32.768-kHz clock source may be used instead of a crystal. In such a case, the clock source is connected to RTC_XI, and RTC_XO is left unconnected.

If the RTC is not used, the RTC_XI pin should be held either low or high, RTC_XO should be left unconnected, RTC_CVDD should be connected to the device CVDD, and RTC_VSS should remain grounded.

Figure 6-71 Clock Source

6.28.2 Real-Time Clock Register Descriptions

Table 6-119 Real-Time Clock (RTC) Registers

BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01C2 3000	SECOND	Seconds Register
0x01C2 3004	MINUTE	Minutes Register
0x01C2 3008	HOUR	Hours Register
0x01C2 300C	DAY	Day of the Month Register
0x01C2 3010	MONTH	Month Register
0x01C2 3014	YEAR	Year Register
0x01C2 3018	DOTW	Day of the Week Register
0x01C2 3020	ALARMSECOND	Alarm Seconds Register
0x01C2 3024	ALARMMINUTE	Alarm Minutes Register
0x01C2 3028	ALARMHOUR	Alarm Hours Register
0x01C2 302C	ALARMDAY	Alarm Days Register
0x01C2 3030	ALARMMONTH	Alarm Months Register
0x01C2 3034	ALARMYEAR	Alarm Years Register
0x01C2 3040	CTRL	Control Register
0x01C2 3044	STATUS	Status Register
0x01C2 3048	INTERRUPT	Interrupt Enable Register
0x01C2 304C	COMPLSB	Compensation (LSB) Register
0x01C2 3050	COMPMSB	Compensation (MSB) Register
0x01C2 3054	OSC	Oscillator Register
0x01C2 3060	SCRATCH0	Scratch 0 (General-Purpose) Register
0x01C2 3064	SCRATCH1	Scratch 1 (General-Purpose) Register
0x01C2 3068	SCRATCH2	Scratch 2 (General-Purpose) Register
0x01C2 306C	KICK0	Kick 0 (Write Protect) Register
0x01C2 3070	KICK1	Kick 1 (Write Protect) Register

6.29 General-Purpose Input/Output (GPIO)

The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. When configured as an output, a write to an internal register can control the state driven on the output pin. When configured as an input, the state of the input is detectable by reading the state of an internal register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices. The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).

The device GPIO peripheral supports the following:

Up to 144 Pins configurable as GPIO
External Interrupt and DMA request Capability
- Every GPIO pin may be configured to generate an interrupt request on detection of rising and/or falling edges on the pin.
- The interrupt requests within each bank are combined (logical or) to create eight unique bank level interrupt requests.
- The bank level interrupt service routine may poll the INTSTATx register for its bank to determine which pin(s) have triggered the interrupt.
- GPIO Banks 0, 1, 2, 3, 4, 5, 6, 7, and 8 Interrupts assigned to DSP Events 65, 41, 49, 52, 54, 59, 62, 72, and 75 respectively
- GPIO Banks 0, 1, 2, 3, 4, and 5 are assigned to EDMA events 6, 7, 22, 23, 28, 29, and 29 respectively on Channel Controller 0 and GPIO Banks 6, 7, and 8 are assigned to EDMA events 16, 17, and 18 respectively on Channel Controller 1.
Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to anther process during GPIO programming).
Separate Input/Output registers
Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can be toggled by direct write to the output register(s).
Output register, when read, reflects output drive status. This, in addition to the input register reflecting pin status and open-drain I/O cell, allows wired logic be implemented.

The memory map for the GPIO registers is shown in Table 6-120.

6.29.1 GPIO Register Description(s)

Table 6-120 GPIO Registers

BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01E2 6000	REV	Peripheral Revision Register
0x01E2 6004	RESERVED	Reserved
0x01E2 6008	BINTEN	GPIO Interrupt Per-Bank Enable Register
GPIO Banks 0 and 1
0x01E2 6010	DIR01	GPIO Banks 0 and 1 Direction Register
0x01E2 6014	OUT_DATA01	GPIO Banks 0 and 1 Output Data Register
0x01E2 6018	SET_DATA01	GPIO Banks 0 and 1 Set Data Register
0x01E2 601C	CLR_DATA01	GPIO Banks 0 and 1 Clear Data Register
0x01E2 6020	IN_DATA01	GPIO Banks 0 and 1 Input Data Register
0x01E2 6024	SET_RIS_TRIG01	GPIO Banks 0 and 1 Set Rising Edge Interrupt Register
0x01E2 6028	CLR_RIS_TRIG01	GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register
0x01E2 602C	SET_FAL_TRIG01	GPIO Banks 0 and 1 Set Falling Edge Interrupt Register
0x01E2 6030	CLR_FAL_TRIG01	GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register
0x01E2 6034	INTSTAT01	GPIO Banks 0 and 1 Interrupt Status Register
GPIO Banks 2 and 3
0x01E2 6038	DIR23	GPIO Banks 2 and 3 Direction Register
0x01E2 603C	OUT_DATA23	GPIO Banks 2 and 3 Output Data Register
0x01E2 6040	SET_DATA23	GPIO Banks 2 and 3 Set Data Register
0x01E2 6044	CLR_DATA23	GPIO Banks 2 and 3 Clear Data Register
0x01E2 6048	IN_DATA23	GPIO Banks 2 and 3 Input Data Register
0x01E2 604C	SET_RIS_TRIG23	GPIO Banks 2 and 3 Set Rising Edge Interrupt Register
0x01E2 6050	CLR_RIS_TRIG23	GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register
0x01E2 6054	SET_FAL_TRIG23	GPIO Banks 2 and 3 Set Falling Edge Interrupt Register
0x01E2 6058	CLR_FAL_TRIG23	GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register
0x01E2 605C	INTSTAT23	GPIO Banks 2 and 3 Interrupt Status Register
GPIO Banks 4 and 5
0x01E2 6060	DIR45	GPIO Banks 4 and 5 Direction Register
0x01E2 6064	OUT_DATA45	GPIO Banks 4 and 5 Output Data Register
0x01E2 6068	SET_DATA45	GPIO Banks 4 and 5 Set Data Register
0x01E2 606C	CLR_DATA45	GPIO Banks 4 and 5 Clear Data Register
0x01E2 6070	IN_DATA45	GPIO Banks 4 and 5 Input Data Register
0x01E2 6074	SET_RIS_TRIG45	GPIO Banks 4 and 5 Set Rising Edge Interrupt Register
0x01E2 6078	CLR_RIS_TRIG45	GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register
0x01E2 607C	SET_FAL_TRIG45	GPIO Banks 4 and 5 Set Falling Edge Interrupt Register
0x01E2 6080	CLR_FAL_TRIG45	GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register
0x01E2 6084	INTSTAT45	GPIO Banks 4 and 5 Interrupt Status Register
GPIO Banks 6 and 7
0x01E2 6088	DIR67	GPIO Banks 6 and 7 Direction Register
0x01E2 608C	OUT_DATA67	GPIO Banks 6 and 7 Output Data Register
0x01E2 6090	SET_DATA67	GPIO Banks 6 and 7 Set Data Register
0x01E2 6094	CLR_DATA67	GPIO Banks 6 and 7 Clear Data Register
0x01E2 6098	IN_DATA67	GPIO Banks 6 and 7 Input Data Register
0x01E2 609C	SET_RIS_TRIG67	GPIO Banks 6 and 7 Set Rising Edge Interrupt Register
0x01E2 60A0	CLR_RIS_TRIG67	GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register
0x01E2 60A4	SET_FAL_TRIG67	GPIO Banks 6 and 7 Set Falling Edge Interrupt Register
0x01E2 60A8	CLR_FAL_TRIG67	GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register
0x01E2 60AC	INTSTAT67	GPIO Banks 6 and 7 Interrupt Status Register
GPIO Bank 8
0x01E2 60B0	DIR8	GPIO Bank 8 Direction Register
0x01E2 60B4	OUT_DATA8	GPIO Bank 8 Output Data Register
0x01E2 60B8	SET_DATA8	GPIO Bank 8 Set Data Register
0x01E2 60BC	CLR_DATA8	GPIO Bank 8 Clear Data Register
0x01E2 60C0	IN_DATA8	GPIO Bank 8 Input Data Register
0x01E2 60C4	SET_RIS_TRIG8	GPIO Bank 8 Set Rising Edge Interrupt Register
0x01E2 60C8	CLR_RIS_TRIG8	GPIO Bank 8 Clear Rising Edge Interrupt Register
0x01E2 60CC	SET_FAL_TRIG8	GPIO Bank 8 Set Falling Edge Interrupt Register
0x01E2 60D0	CLR_FAL_TRIG8	GPIO Bank 8 Clear Falling Edge Interrupt Register
0x01E2 60D4	INTSTAT8	GPIO Bank 8 Interrupt Status Register

6.29.2 GPIO Peripheral Input/Output Electrical Data/Timing

Table 6-121 Timing Requirements for GPIO Inputs⁽¹⁾ (see Figure 6-72)

NO.			1.3V, 1.2V, 1.1V, 1.0V		UNIT
NO.			MIN	MAX	UNIT
1	t_w(GPIH)	Pulse duration, GPn[m] as input high	2C⁽¹⁾ ⁽²⁾		ns
2	t_w(GPIL)	Pulse duration, GPn[m] as input low	2C⁽¹⁾ ⁽²⁾		ns

(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the device recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow the device enough time to access the GPIO register through the internal bus.

(2) C=SYSCLK4 period in ns.

Table 6-122 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 6-72)

NO.	PARAMETER		1.3V, 1.2V, 1.1V, 1.0V		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
3	t_w(GPOH)	Pulse duration, GPn[m] as output high	2C⁽¹⁾ ⁽²⁾		ns
4	t_w(GPOL)	Pulse duration, GPn[m] as output low	2C⁽¹⁾ ⁽²⁾		ns

(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO is dependent upon internal bus activity.

(2) C=SYSCLK4 period in ns.

Figure 6-72 GPIO Port Timing

6.29.3 GPIO Peripheral External Interrupts Electrical Data/Timing

Table 6-123 Timing Requirements for External Interrupts⁽¹⁾ (see Figure 6-73)

NO.			1.3V, 1.2V, 1.1V, 1.0V		UNIT
NO.			MIN	MAX	UNIT
1	t_w(ILOW)	Width of the external interrupt pulse low	2C⁽¹⁾ ⁽²⁾		ns
2	t_w(IHIGH)	Width of the external interrupt pulse high	2C⁽¹⁾ ⁽²⁾		ns

(1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have the device recognize the GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow the device enough time to access the GPIO register through the internal bus.

(2) C=SYSCLK4 period in ns.

Figure 6-73 GPIO External Interrupt Timing

6.30 Programmable Real-Time Unit Subsystem (PRUSS)

The Programmable Real-Time Unit Subsystem (PRUSS) consists of

Two Programmable Real-Time Units (PRU0 and PRU1) and their associated memories
An Interrupt Controller (INTC) for handling system interrupt events. The INTC also supports posting events back to the device level host CPU.
A Switched Central Resource (SCR) for connecting the various internal and external masters to the resources inside the PRUSS.

The two PRUs can operate completely independently or in coordination with each other. The PRUs can also work in coordination with the device level host CPU. This is determined by the nature of the program which is loaded into the PRUs instruction memory. Several different signaling mechanisms are available between the two PRUs and the device level host CPU.

The PRUs are optimized for performing embedded tasks that require manipulation of packed memory mapped data structures, handling of system events that have tight realtime constraints and interfacing with systems external to the device.

The PRUSS comprises various distinct addressable regions. Externally the subsystem presents a single 64Kbyte range of addresses. The internal interconnect bus (also called switched central resource, or SCR) of the PRUSS decodes accesses for each of the individual regions. The PRUSS memory map is documented in Table 6-124 and in Table 6-125. Note that these two memory maps are implemented inside the PRUSS and are local to the components of the PRUSS.

Table 6-124 Programmable Real-Time Unit Subsystem (PRUSS) Local Instruction Space Memory Map

BYTE ADDRESS	PRU0	PRU1
0x0000 0000 - 0x0000 0FFF	PRU0 Instruction RAM	PRU1 Instruction RAM

Table 6-125 Programmable Real-Time Unit Subsystem (PRUSS) Local Data Space Memory Map

BYTE ADDRESS	PRU0	PRU1
0x0000 0000 - 0x0000 01FF	Data RAM 0⁽¹⁾	Data RAM 1⁽¹⁾
0x0000 0200 - 0x0000 1FFF	Reserved	Reserved
0x0000 2000 - 0x0000 21FF	Data RAM 1⁽¹⁾	Data RAM 0⁽¹⁾
0x0000 2200 - 0x0000 3FFF	Reserved	Reserved
0x0000 4000 - 0x0000 6FFF	INTC Registers	INTC Registers
0x0000 7000 - 0x0000 73FF	PRU0 Control Registers	PRU0 Control Registers
0x0000 7400 - 0x0000 77FF	Reserved	Reserved
0x0000 7800 - 0x0000 7BFF	PRU1 Control Registers	PRU1 Control Registers
0x0000 7C00 - 0xFFFF FFFF	Reserved	Reserved

(1) Note that PRU0 accesses Data RAM0 at address 0x0000 0000, also PRU1 accesses Data RAM1 at address 0x0000 0000. Data RAM0 is intended to be the primary data memory for PRU0 and Data RAM1 is intended to be the primary data memory for PRU1. However for passing information between PRUs, each PRU can access the data ram of the ‘other’ PRU through address 0x0000 2000.

The global view of the PRUSS internal memories and control ports is documented in Table 6-126. The offset addresses of each region are implemented inside the PRUSS but the global device memory mapping places the PRUSS slave port in the address range 0x01C3 0000-0x01C3 FFFF. The PRU0 and PRU1 can use either the local or global addresses to access their internal memories, but using the local addresses will provide access time several cycles faster than using the global addresses. This is because when accessing via the global address the access needs to be routed through the switch fabric outside PRUSS and back in through the PRUSS slave port.

Table 6-126 Programmable Real-Time Unit Subsystem (PRUSS) Global Memory Map

BYTE ADDRESS	REGION
0x01C3 0000 - 0x01C3 01FF	Data RAM 0
0x01C3 0200 - 0x01C3 1FFF	Reserved
0x01C3 2000 - 0x01C3 21FF	Data RAM 1
0x01C3 2200 - 0x01C3 3FFF	Reserved
0x01C3 4000 - 0x01C3 6FFF	INTC Registers
0x01C3 7000 - 0x01C3 73FF	PRU0 Control Registers
0x01C3 7400 - 0x01C3 77FF	PRU0 Debug Registers
0x01C3 7800 - 0x01C3 7BFF	PRU1 Control Registers
0x01C3 7C00 - 0x01C3 7FFF	PRU1 Debug Registers
0x01C3 8000 - 0x01C3 8FFF	PRU0 Instruction RAM
0x01C3 9000 - 0x01C3 BFFF	Reserved
0x01C3 C000 - 0x01C3 CFFF	PRU1 Instruction RAM
0x01C3 D000 - 0x01C3 FFFF	Reserved

Each of the PRUs can access the rest of the device memory (including memory mapped peripheral and configuration registers) using the global memory space addresses

6.30.1 PRUSS Register Descriptions

Table 6-127 Programmable Real-Time Unit Subsystem (PRUSS) Control / Status Registers

PRU0 BYTE ADDRESS	PRU1 BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01C3 7000	0x01C3 7800	CONTROL	PRU Control Register
0x01C3 7004	0x01C3 7804	STATUS	PRU Status Register
0x01C3 7008	0x01C3 7808	WAKEUP	PRU Wakeup Enable Register
0x01C3 700C	0x01C3 780C	CYCLCNT	PRU Cycle Count
0x01C3 7010	0x01C3 7810	STALLCNT	PRU Stall Count
0x01C3 7020	0x01C3 7820	CONTABBLKIDX0	PRU Constant Table Block Index Register 0
0x01C3 7028	0x01C3 7828	CONTABPROPTR0	PRU Constant Table Programmable Pointer Register 0
0x01C3 702C	0x01C3 782C	CONTABPROPTR1	PRU Constant Table Programmable Pointer Register 1
0x01C37400 - 0x01C3747C	0x01C3 7C00 - 0x01C3 7C7C	INTGPR0 – INTGPR31	PRU Internal General Purpose Register 0 (for Debug)
0x01C37480 - 0x01C374FC	0x01C3 7C80 - 0x01C3 7CFC	INTCTER0 – INTCTER31	PRU Internal General Purpose Register 0 (for Debug)

Table 6-128 Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC) Registers

BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION
0x01C3 4000	REVID	Revision ID Register
0x01C3 4004	CONTROL	Control Register
0x01C3 4010	GLBLEN	Global Enable Register
0x01C3 401C	GLBLNSTLVL	Global Nesting Level Register
0x01C3 4020	STATIDXSET	System Interrupt Status Indexed Set Register
0x01C3 4024	STATIDXCLR	System Interrupt Status Indexed Clear Register
0x01C3 4028	ENIDXSET	System Interrupt Enable Indexed Set Register
0x01C3 402C	ENIDXCLR	System Interrupt Enable Indexed Clear Register
0x01C3 4034	HSTINTENIDXSET	Host Interrupt Enable Indexed Set Register
0x01C3 4038	HSTINTENIDXCLR	Host Interrupt Enable Indexed Clear Register
0x01C3 4080	GLBLPRIIDX	Global Prioritized Index Register
0x01C3 4200	STATSETINT0	System Interrupt Status Raw/Set Register 0
0x01C3 4204	STATSETINT1	System Interrupt Status Raw/Set Register 1
0x01C3 4280	STATCLRINT0	System Interrupt Status Enabled/Clear Register 0
0x01C3 4284	STATCLRINT1	System Interrupt Status Enabled/Clear Register 1
0x01C3 4300	ENABLESET0	System Interrupt Enable Set Register 0
0x01C3 4304	ENABLESET1	System Interrupt Enable Set Register 1
0x01C3 4380	ENABLECLR0	System Interrupt Enable Clear Register 0
0x01C3 4384	ENABLECLR1	System Interrupt Enable Clear Register 1
0x01C3 4400 - 0x01C3 4440	CHANMAP0 - CHANMAP15	Channel Map Registers 0-15
0x01C3 4800 - 0x01C3 4808	HOSTMAP0 - HOSTMAP2	Host Map Register 0-2
0x01C3 4900 - 0x01C3 4928	HOSTINTPRIIDX0 - HOSTINTPRIIDX9	Host Interrupt Prioritized Index Registers 0-9
0x01C3 4D00	POLARITY0	System Interrupt Polarity Register 0
0x01C3 4D04	POLARITY1	System Interrupt Polarity Register 1
0x01C3 4D80	TYPE0	System Interrupt Type Register 0
0x01C3 4D84	TYPE1	System Interrupt Type Register 1
0x01C3 5100 - 0x01C3 5128	HOSTINTNSTLVL0-HOSTINTNSTLVL9	Host Interrupt Nesting Level Registers 0-9
0x01C3 5500	HOSTINTEN	Host Interrupt Enable Register

6.31 Emulation Logic

The debug capabilities and features for DSP are as shown below.

DSP:

Basic Debug
- Execution Control
- System Visibility
Real-Time Debug
- Interrupts serviced while halted
- Low/non-intrusive system visibility while running

Advanced Debug
- Global Start
- Global Stop
- Specify targeted memory level(s) during memory accesses
- HSRTDX (High Speed Real Time Data eXchange)

Advanced System Control
- Subsystem reset via debug
- Peripheral notification of debug events
- Cache-coherent debug accesses

Analysis Actions
- Stop program execution
- Generate debug interrupt
- Benchmarking with counters
- External trigger generation
- Debug state machine state transition
- Combinational and Sequential event generation

Analysis Events
- Program event detection
- Data event detection
- External trigger Detection
- System event detection (i.e. cache miss)
- Debug state machine state detection

Analysis Configuration
- Application access
- Debugger access

Table 6-129 DSP Debug Features

Category	Hardware Feature	Availability
Basic Debug	Software breakpoint	Unlimited
	Hardware breakpoint	Up to 10 HWBPs, including:
		4 precise⁽¹⁾ HWBPs inside DSP core and one of them is associated with a counter.
		2 imprecise⁽¹⁾ HWBPs from AET.
		4 imprecise⁽¹⁾ HWBPs from AET which are shared for watch point.
Analysis	Watch point	Up to 4 watch points, which are shared with HWBPs, and can also be used as 2 watch points with data (32 bits)
	Watch point with Data	Up to 2, Which can also be used as 4 watch points.
	Counters/timers	1x64-bits (cycle only) + 2x32-bits (water mark counters)
	External Event Trigger In	1
	External Event Trigger Out	1

(1) Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints will halt the processor some number of cycles after the selected instruction depending on device conditions.

6.31.1 JTAG Port Description

The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS, TDI, and TDO).

TRST holds the debug and boundary scan logic in reset (normal DSP operation) when pulled low (its default state). Since TRST has an internal pull-down resistor, this ensures that at power up the device functions in its normal (non-test) operation mode if TRST is not connected. Otherwise, TRST should be driven inactive by the emulator or boundary scan controller. Boundary scan test cannot be performed while the TRST pin is pulled low.

Table 6-130 JTAG Port Description

PIN	TYPE	NAME	DESCRIPTION
TRST	I	Test Logic Reset	When asserted (active low) causes all test and debug logic in the device to be reset along with the IEEE 1149.1 interface
TCK	I	Test Clock	This is the test clock used to drive an IEEE 1149.1 TAP state machine and logic.
TMS	I	Test Mode Select	Directs the next state of the IEEE 1149.1 test access port state machine
TDI	I	Test Data Input	Scan data input to the device
TDO	O	Test Data Output	Scan data output of the device
EMU0	I/O	Emulation 0	Channel 0 trigger + HSRTDX
EMU1	I/O	Emulation 1	Channel 1 trigger + HSRTDX

6.31.2 Scan Chain Configuration Parameters

Table 6-131 shows the TAP configuration details required to configure the router/emulator for this device.

Table 6-131 JTAG Port Description

Router Port ID	Default TAP	TAP Name	Tap IR Length
17	No	C674x	38
19	No	ETB	4

The router is revision C and has a 6-bit IR length.

6.31.3 Initial Scan Chain Configuration

The first level of debug interface that sees the scan controller is the TAP router module. The debugger can configure the TAP router for serially linking up to 16 TAP controllers or individually scanning one of the TAP controllers without disrupting the IR state of the other TAPs.

6.31.4 IEEE 1149.1 JTAG

The JTAG ^{IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.} interface is used for BSDL testing and emulation of the device.

1. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

The device requires that both TRST and RESET be asserted upon power up to be properly initialized. While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required for proper operation.

RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan instructions work correctly independent of current state of RESET.

For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the device's internal emulation logic will always be properly initialized.

JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST.

When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations.

6.31.4.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)

Table 6-132 DEVIDR0 Register

BYTE ADDRESS	ACRONYM	REGISTER DESCRIPTION	COMMENTS
0x01C1 4018	DEVIDR0	JTAG Identification Register	Read-only. Provides 32-bit JTAG ID of the device.

The JTAG ID register is a read-only register that identifies the JTAG/Device ID. For the device, the JTAG ID register resides at address location 0x01C1 4018. The register hex value for each silicon revision is:

0x0B7D 102F for silicon revision 1.x
0x1B7D 102F for silicon revision 2.x

For the actual register bit names and their associated bit field descriptions, see Figure 6-74 and Table 6-133.

Figure 6-74 JTAG ID (DEVIDR0) Register Description - Register Value

31-28	27-12	11-1	0
VARIANT (4-Bit)	PART NUMBER (16-Bit)	MANUFACTURER (11-Bit)	LSB
R-xxxx	R-1011 0111 1101 0001	R-0000 0010 111	R-1

LEGEND: R = Read, W = Write, n = value at reset

Table 6-133 JTAG ID Register Selection Bit Descriptions

BIT	NAME	DESCRIPTION
31:28	VARIANT	Variant (4-Bit) value
27:12	PART NUMBER	Part Number (16-Bit) value
11-1	MANUFACTURER	Manufacturer (11-Bit) value
0	LSB	LSB. This bit is read as a "1".

6.31.4.2 JTAG Test-Port Electrical Data/Timing

Table 6-134 Timing Requirements for JTAG Test Port (see Figure 6-75)

No.			1.3V, 1.2V		1.1V		1.0V		UNIT
No.			MIN	MAX	MIN	MAX	MIN	MAX	UNIT
1	t_c(TCK)	Cycle time, TCK	40		50		66.6		ns
2	t_w(TCKH)	Pulse duration, TCK high	16		20		26.6		ns
3	t_w(TCKL)	Pulse duration, TCK low	16		20		26.6		ns
4	t_{su(TDIV-TCKH)}	Setup time, TDI/TMS/TRST valid before TCK high	4		4		4		ns
5	t_{h(TCLKH-TDIV)}	Hold time, TDI/TMS/TRST valid after TCK high	4		6		8		ns

Table 6-135 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 6-75)

No.	PARAMETER		1.3V, 1.2V		1.1V		1.0V		UNIT
No.	PARAMETER		MIN	MAX	MIN	MAX	MIN	MAX	UNIT
6	t_d(TCKL-TDOV)	Delay time, TCK low to TDO valid		18		23		31	ns

Figure 6-75 JTAG Test-Port Timing

6.31.5 JTAG 1149.1 Boundary Scan Considerations

To use boundary scan, the following sequence should be followed:

Execute a valid reset sequence and exit reset
Wait at least 6000 OSCIN clock cycles
Enter boundary scan mode using the JTAG pins

No specific value is required on the EMU0 and EMU1 pins for boundary scan testing. If TRST is not driven by the boundary scan tool or tester, TRST should be externally pulled high during boundary scan testing.

Package Options

Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6 Peripheral Information and Electrical Specifications

6.1 Parameter Information

6.1.1 Parameter Information Device-Specific Information

6.1.1.1 Signal Transition Levels

6.2 Recommended Clock and Control Signal Transition Behavior

6.3 Power Supplies

6.3.1 Power-On Sequence

6.3.2 Power-Off Sequence

6.4 Reset

6.4.1 Power-On Reset (POR)

6.4.2 Warm Reset

6.4.3 Reset Electrical Data Timings

Table 6-1 Reset Timing Requirements ((1), (2))

6.5 Crystal Oscillator or External Clock Input

Table 6-2 Oscillator Timing Requirements

Table 6-3 OSCIN Timing Requirements for an Externally Driven Clock

6.6 Clock PLLs

6.6.1 PLL Device-Specific Information

Table 6-4 Allowed PLL Operating Conditions (PLL0 and PLL1)

6.6.2 Device Clock Generation

6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)

Table 6-5 Maximum Internal Clock Frequencies at Each Voltage Operating Point

6.7 Interrupts

6.7.1 DSP Interrupts

Table 6-6 C6746 DSP Interrupts

Table 6-7 C674x DSP Interrupt Controller Registers

6.8 Power and Sleep Controller (PSC)

Table 6-8 Power and Sleep Controller (PSC) Registers

6.8.1 Power Domain and Module Topology

Table 6-9 PSC0 Default Module Configuration

Table 6-10 PSC1 Default Module Configuration

6.8.1.1 Power Domain States

6.8.1.2 Module States

Table 6-11 Module States

6.9 Enhanced Direct Memory Access Controller (EDMA3)

6.9.1 EDMA3 Channel Synchronization Events

Table 6-12 EDMA Synchronization Events

6.9.2 EDMA3 Peripheral Register Descriptions

Table 6-13 EDMA3 Channel Controller (EDMA3CC) Registers

Table 6-14 EDMA3 Transfer Controller (EDMA3TC) Registers

Table 6-15 EDMA3 Parameter Set RAM

Table 6-16 Parameter Set Entries

6.10 External Memory Interface A (EMIFA)

6.10.1 EMIFA Asynchronous Memory Support

6.10.2 EMIFA Synchronous DRAM Memory Support

Table 6-17 EMIFA Supported SDRAM Configurations(1)

6.10.3 EMIFA SDRAM Loading Limitations

6.10.4 EMIFA Connection Examples

6.10.5 External Memory Interface Register Descriptions

Table 6-18 External Memory Interface (EMIFA) Registers

6.10.6 EMIFA Electrical Data/Timing

Table 6-19 Timing Requirements for EMIFA SDRAM Interface

Table 6-20 Switching Characteristics for EMIFA SDRAM Interface

Table 6-21 Timing Requirements for EMIFA Asynchronous Memory Interface (1)

Table 6-22 Switching Characteristics for EMIFA Asynchronous Memory Interface (1) (2) (3)

6.11 DDR2/mDDR Memory Controller

6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing

Table 6-23 Switching Characteristics Over Recommended Operating Conditions for DDR2/mDDR Memory Controller

6.11.2 DDR2/mDDR Memory Controller Register Description(s)

Table 6-24 DDR2/mDDR Memory Controller Registers

6.11.3 DDR2/mDDR Interface

6.11.3.1 DDR2/mDDR Interface Schematic

6.11.3.2 Compatible JEDEC DDR2/mDDR Devices

Table 6-25 Compatible JEDEC DDR2/mDDR Devices

6.11.3.3 PCB Stackup

Table 6-26 Device Minimum PCB Stack Up

Table 6-27 PCB Stack Up Specifications

6.11.3.4 Placement

Table 6-28 Placement Specifications(1)(2)

6.11.3.5 DDR2/mDDR Keep Out Region

6.11.3.6 Bulk Bypass Capacitors

Table 6-29 Bulk Bypass Capacitors

6.11.3.7 High-Speed Bypass Capacitors

Table 6-30 High-Speed Bypass Capacitors

6.11.3.8 Net Classes

Table 6-31 Clock Net Class Definitions

Table 6-1 Reset Timing Requirements (⁽¹⁾, ⁽²⁾)

Table 6-17 EMIFA Supported SDRAM Configurations⁽¹⁾

Table 6-21 Timing Requirements for EMIFA Asynchronous Memory Interface ⁽¹⁾

Table 6-22 Switching Characteristics for EMIFA Asynchronous Memory Interface ⁽¹⁾ ⁽²⁾ ⁽³⁾

Table 6-28 Placement Specifications⁽¹⁾⁽²⁾

Table 6-33 DDR2/mDDR Signal Terminations⁽¹⁾⁽²⁾⁽³⁾

Table 6-40 Timing Requirements for MMC/SD
(see Figure 6-27 and Figure 6-29)

Table 6-45 Timing Requirements for McASP0 (1.3V, 1.2V, 1.1V)⁽²⁾⁽⁵⁾

Table 6-46 Timing Requirements for McASP0 (1.0V)⁽²⁾⁽⁵⁾

Table 6-47 Switching Characteristics for McASP0 (1.3V, 1.2V, 1.1V)⁽¹⁾

Table 6-48 Switching Characteristics for McASP0 (1.0V)⁽¹⁾

Table 6-50 Timing Requirements for McBSP0 [1.3V, 1.2V, 1.1V]⁽¹⁾ (see Figure 6-33)

Table 6-51 Timing Requirements for McBSP0 [1.0V]⁽¹⁾ (see Figure 6-33)

Table 6-52 Switching Characteristics for McBSP0 [1.3V, 1.2V, 1.1V]⁽¹⁾⁽²⁾
(see Figure 6-33)

Table 6-53 Switching Characteristics for McBSP0 [1.0V]⁽¹⁾ ⁽²⁾
(see Figure 6-33)

Table 6-54 Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V]⁽¹⁾ (see Figure 6-33)

Table 6-55 Timing Requirements for McBSP1 [1.0V]⁽¹⁾ (see Figure 6-33)

Table 6-56 Switching Characteristics for McBSP1 [1.3V, 1.2V, 1.1V]⁽¹⁾ ⁽²⁾
(see Figure 6-33)

Table 6-57 Switching Characteristics for McBSP1 [1.0V]⁽¹⁾ ⁽²⁾
(see Figure 6-33)

Table 6-61 General Timing Requirements for SPI0 Master Modes⁽¹⁾

Table 6-62 General Timing Requirements for SPI0 Slave Modes⁽¹⁾

Table 6-63 Additional SPI0 Master Timings, 4-Pin Enable Option ⁽⁵⁾⁽¹⁾⁽²⁾

Table 6-64 Additional SPI0 Master Timings, 4-Pin Chip Select Option ⁽⁷⁾⁽¹⁾⁽²⁾

Table 6-65 Additional SPI0 Master Timings, 5-Pin Option ⁽¹⁰⁾⁽¹⁾⁽²⁾

Table 6-66 Additional SPI0 Slave Timings, 4-Pin Enable Option ⁽³⁾⁽¹⁾⁽²⁾

Table 6-67 Additional SPI0 Slave Timings, 4-Pin Chip Select Option ⁽³⁾⁽¹⁾⁽²⁾

Table 6-68 Additional SPI0 Slave Timings, 5-Pin Option ⁽⁴⁾⁽¹⁾⁽²⁾

Table 6-69 General Timing Requirements for SPI1 Master Modes⁽¹⁾

Table 6-70 General Timing Requirements for SPI1 Slave Modes⁽¹⁾

Table 6-71 Additional⁽⁵⁾ SPI1 Master Timings, 4-Pin Enable Option⁽¹⁾⁽²⁾

Table 6-72 Additional⁽⁷⁾ SPI1 Master Timings, 4-Pin Chip Select Option⁽¹⁾ ⁽²⁾

Table 6-73 Additional⁽¹⁰⁾ SPI1 Master Timings, 5-Pin Option⁽¹⁾⁽²⁾

Table 6-74 Additional⁽³⁾ SPI1 Slave Timings, 4-Pin Enable Option⁽¹⁾⁽²⁾

Table 6-75 Additional⁽³⁾ SPI1 Slave Timings, 4-Pin Chip Select Option⁽¹⁾⁽²⁾

Table 6-76 Additional⁽⁴⁾ SPI1 Slave Timings, 5-Pin Option⁽¹⁾⁽²⁾