SPRS614F March   2011  – March 2015 TMS320DM8165 , TMS320DM8167 , TMS320DM8168

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 ARM Subsystem
      1. 3.2.1 ARM Cortex-A8 RISC Processor
      2. 3.2.2 Embedded Trace Module (ETM)
      3. 3.2.3 ARM Cortex-A8 Interrupt Controller (AINTC)
      4. 3.2.4 System Interconnect
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 System Memory Management Unit (System MMU)
        1. 3.3.2.1 System MMU Registers
    4. 3.4 Media Controller
    5. 3.5 High-Definition Video Image Coprocessor 2 (HDVICP2)
    6. 3.6 Inter-Processor Communication
      1. 3.6.1 Mailbox Module
        1. 3.6.1.1 Mailbox Registers
      2. 3.6.2 Spinlock Module
        1. 3.6.2.1 Spinlock Registers
    7. 3.7 Power, Reset and Clock Management (PRCM) Module
    8. 3.8 SGX530 (DM8168 only)
    9. 3.9 Memory Map Summary
      1. 3.9.1 L3 Memory Map
      2. 3.9.2 L4 Memory Map
        1. 3.9.2.1 L4 Standard Peripheral
        2. 3.9.2.2 L4 High-Speed Peripheral
      3. 3.9.3 TILER Extended Addressing Map
      4. 3.9.4 Cortex™-A8 Memory Map
      5. 3.9.5 C674x Memory Map
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Assignments
      1. 4.1.1 Pin Map (Bottom View)
    2. 4.2 Terminal Functions
      1. 4.2.1  Boot Configuration
      2. 4.2.2  DDR2 and DDR3 Memory Controller Signals
      3. 4.2.3  Ethernet Media Access Controller (EMAC) Signals
      4. 4.2.4  General-Purpose Input/Output (GPIO) Signals
      5. 4.2.5  General-Purpose Memory Controller (GPMC) Signals
      6. 4.2.6  High-Definition Multimedia Interface (HDMI) Signals
      7. 4.2.7  Inter-Integrated Circuit (I2C) Signals
      8. 4.2.8  Multichannel Audio Serial Port Signals
      9. 4.2.9  Multichannel Buffered Serial Port Signals
      10. 4.2.10 Oscillator/Phase-Locked Loop (PLL) Signals
      11. 4.2.11 Peripheral Component Interconnect Express (PCIe) Signals
      12. 4.2.12 Reset, Interrupts, and JTAG Interface Signals
      13. 4.2.13 Secure Digital/Secure Digital Input Output (SD/SDIO) Signals
      14. 4.2.14 Serial ATA Signals
      15. 4.2.15 Serial Peripheral Digital Interconnect Format (SPI) Signals
      16. 4.2.16 Timer Signals
      17. 4.2.17 Universal Asynchronous Receiver/Transmitter (UART) Signals
      18. 4.2.18 Universal Serial Bus (USB) Signals
      19. 4.2.19 Video Input Signals
      20. 4.2.20 Digital Video Output Signals
      21. 4.2.21 Analog Video Output Signals
      22. 4.2.22 Reserved Pins
      23. 4.2.23 Supply Voltages
      24. 4.2.24 Ground Pins (VSS)
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings (Unless Otherwise Noted)
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Resistance Characteristics
  6. 6 Device Configurations
    1. 6.1 Control Module
    2. 6.2 Revision Identification
    3. 6.3 Debugging Considerations
      1. 6.3.1 Pullup and Pulldown Resistors
    4. 6.4 Boot Sequence
      1. 6.4.1 Boot Mode Registers
    5. 6.5 Pin Multiplexing Control
      1. 6.5.1 PINCTRLx Register Descriptions
    6. 6.6 How to Handle Unused Pins
  7. 7 System Interconnect
    1. 7.1 L3 Interconnect
    2. 7.2 L4 Interconnect
  8. 8 Power, Reset, Clocking, and Interrupts
    1. 8.1 Power Supplies
      1. 8.1.1 Voltage and Power Domains
      2. 8.1.2 Power Domains
      3. 8.1.3 1-V AVS and 1-V Constant Power Domains
      4. 8.1.4 SmartReflex™
      5. 8.1.5 Memory Power Management
      6. 8.1.6 IO Power-Down Modes
      7. 8.1.7 Supply Sequencing
      8. 8.1.8 Power-Supply Decoupling
    2. 8.2 Reset
      1. 8.2.1  System-Level Reset Sources
      2. 8.2.2  Power-On Reset (POR pin)
      3. 8.2.3  External Warm Reset (RESET pin)
      4. 8.2.4  Emulation Warm Reset
      5. 8.2.5  Watchdog Reset
      6. 8.2.6  Software Global Cold Reset
      7. 8.2.7  Software Global Warm Reset
      8. 8.2.8  Test Reset (TRST pin)
      9. 8.2.9  Local Reset
      10. 8.2.10 Reset Priority
      11. 8.2.11 Reset Status Register
      12. 8.2.12 PCIe Reset Isolation
      13. 8.2.13 RSTOUT
      14. 8.2.14 Effect of Reset on Emulation and Trace
      15. 8.2.15 Reset During Power Domain Switching
      16. 8.2.16 Pin Behaviors at Reset
      17. 8.2.17 Reset Electrical Data and Timing
    3. 8.3 Clocking
      1. 8.3.1 Device Clock Inputs
        1. 8.3.1.1 Using the Internal Oscillators
      2. 8.3.2 SERDES_CLKN and SERDES_CLKP Input Clock
      3. 8.3.3 CLKIN32 Input Clock
      4. 8.3.4 PLLs
        1. 8.3.4.1 PLL Programming Limits
        2. 8.3.4.2 PLL Power Supply Filtering
        3. 8.3.4.3 PLL Locking Sequence
        4. 8.3.4.4 PLL Registers
      5. 8.3.5 SYSCLKs
      6. 8.3.6 Module Clocks
      7. 8.3.7 Output Clock Select Logic
    4. 8.4 Interrupts
      1. 8.4.1 Interrupt Summary List
      2. 8.4.2 Cortex™-A8 Interrupts
      3. 8.4.3 C674x Interrupts
  9. 9 Peripheral Information and Timings
    1. 9.1  Parameter Information
      1. 9.1.1 1.8-V and 3.3-V Signal Transition Levels
      2. 9.1.2 3.3-V Signal Transition Rates
      3. 9.1.3 Timing Parameters and Board Routing Analysis
    2. 9.2  Recommended Clock and Control Signal Transition Behavior
    3. 9.3  DDR2 and DDR3 Memory Controller
      1. 9.3.1 DDR2 Routing Specifications
        1. 9.3.1.1 Board Designs
        2. 9.3.1.2 DDR2 Interface
          1. 9.3.1.2.1  DDR2 Interface Schematic
          2. 9.3.1.2.2  Compatible JEDEC DDR2 Devices
          3. 9.3.1.2.3  PCB Stackup
          4. 9.3.1.2.4  Placement
          5. 9.3.1.2.5  DDR2 Keepout Region
          6. 9.3.1.2.6  Bulk Bypass Capacitors
          7. 9.3.1.2.7  High-Speed Bypass Capacitors
          8. 9.3.1.2.8  Net Classes
          9. 9.3.1.2.9  DDR2 Signal Termination
          10. 9.3.1.2.10 VREFSSTL_DDR Routing
        3. 9.3.1.3 DDR2 CK and ADDR_CTRL Routing
      2. 9.3.2 DDR3 Routing Specifications
        1. 9.3.2.1  Board Designs
          1. 9.3.2.1.1 DDR3 versus DDR2
        2. 9.3.2.2  DDR3 Device Combinations
          1. 9.3.2.2.1 DDR3 EMIFs
        3. 9.3.2.3  DDR3 Interface Schematic
          1. 9.3.2.3.1 32-Bit DDR3 Interface
          2. 9.3.2.3.2 16-Bit DDR3 Interface
        4. 9.3.2.4  Compatible JEDEC DDR3 Devices
        5. 9.3.2.5  PCB Stackup
        6. 9.3.2.6  Placement
        7. 9.3.2.7  DDR3 Keepout Region
        8. 9.3.2.8  Bulk Bypass Capacitors
        9. 9.3.2.9  High-Speed Bypass Capacitors
          1. 9.3.2.9.1 Return Current Bypass Capacitors
        10. 9.3.2.10 Net Classes
        11. 9.3.2.11 DDR3 Signal Termination
        12. 9.3.2.12 VREFSSTL_DDR Routing
        13. 9.3.2.13 VTT
        14. 9.3.2.14 CK and ADDR_CTRL Topologies and Routing Definition
          1. 9.3.2.14.1 Four DDR3 Devices
            1. 9.3.2.14.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 9.3.2.14.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 9.3.2.14.2 Two DDR3 Devices
            1. 9.3.2.14.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 9.3.2.14.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 9.3.2.14.3 One DDR3 Device
            1. 9.3.2.14.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 9.3.2.14.3.2 CK and ADDR_CTRL Routing, One DDR3 Device
        15. 9.3.2.15 Data Topologies and Routing Definition
          1. 9.3.2.15.1 DQS, DQ and DM Topologies, Any Number of Allowed DDR3 Devices
          2. 9.3.2.15.2 DQS, DQ and DM Routing, Any Number of Allowed DDR3 Devices
        16. 9.3.2.16 Routing Specification
          1. 9.3.2.16.1 CK and ADDR_CTRL Routing Specification
          2. 9.3.2.16.2 DQS and DQ Routing Specification
      3. 9.3.3 DDR2 and DDR3 Memory Controller Register Descriptions
      4. 9.3.4 DDR2 and DDR3 PHY Register Descriptions
      5. 9.3.5 DDR2 and DDR3 Memory Controller Electrical Data and Timing
    4. 9.4  Emulation Features and Capability
      1. 9.4.1 Advanced Event Triggering (AET)
      2. 9.4.2 Trace
      3. 9.4.3 IEEE 1149.1 JTAG
        1. 9.4.3.1 JTAG ID (JTAGID) Register Description
        2. 9.4.3.2 JTAG Electrical Data and Timing
      4. 9.4.4 IEEE 1149.7 cJTAG
    5. 9.5  Enhanced Direct Memory Access (EDMA) Controller
      1. 9.5.1 EDMA Channel Synchronization Events
      2. 9.5.2 EDMA Peripheral Register Descriptions
    6. 9.6  Ethernet Media Access Controller (EMAC)
      1. 9.6.1 EMAC Peripheral Register Descriptions
      2. 9.6.2 EMAC Electrical Data and Timing
      3. 9.6.3 Management Data Input and Output (MDIO)
        1. 9.6.3.1 MDIO Peripheral Register Descriptions
        2. 9.6.3.2 MDIO Electrical Data and Timing
    7. 9.7  General-Purpose Input and Output (GPIO)
      1. 9.7.1 GPIO Peripheral Register Descriptions
      2. 9.7.2 GPIO Electrical Data and Timing
    8. 9.8  General-Purpose Memory Controller (GPMC) and Error Locator Module (ELM)
      1. 9.8.1 GPMC and ELM Peripheral Register Descriptions
      2. 9.8.2 GPMC Electrical Data and Timing
        1. 9.8.2.1 GPMC and NOR Flash Interface Synchronous Mode Timing
        2. 9.8.2.2 GPMC and NOR Flash Interface Asynchronous Mode Timing
        3. 9.8.2.3 GPMC and NAND Flash Interface Asynchronous Mode Timing
    9. 9.9  High-Definition Multimedia Interface (HDMI)
      1. 9.9.1 HDMI Interface Design Specifications
        1. 9.9.1.1 HDMI Interface Schematic
        2. 9.9.1.2 TMDS Routing
        3. 9.9.1.3 DDC Signals
        4. 9.9.1.4 HDMI ESD Protection Device (Required)
        5. 9.9.1.5 PCB Stackup Specifications
        6. 9.9.1.6 Grounding
      2. 9.9.2 HDMI Peripheral Register Descriptions
    10. 9.10 High-Definition Video Processing Subsystem (HDVPSS)
      1. 9.10.1 HDVPSS Electrical Data and Timing
      2. 9.10.2 Video DAC Guidelines and Electrical Data and Timing
    11. 9.11 Inter-Integrated Circuit (I2C)
      1. 9.11.1 I2C Peripheral Register Descriptions
      2. 9.11.2 I2C Electrical Data and Timing
    12. 9.12 Multichannel Audio Serial Port (McASP)
      1. 9.12.1 McASP Device-Specific Information
      2. 9.12.2 McASP0, McASP1, and McASP2 Peripheral Register Descriptions
      3. 9.12.3 McASP Electrical Data and Timing
    13. 9.13 Multichannel Buffered Serial Port (McBSP)
      1. 9.13.1 McBSP Peripheral Registers
      2. 9.13.2 McBSP Electrical Data and Timing
    14. 9.14 Peripheral Component Interconnect Express (PCIe)
      1. 9.14.1 PCIe Design and Layout Specifications
        1. 9.14.1.1 Clock Source
        2. 9.14.1.2 PCIe Connections and Interface Compliance
          1. 9.14.1.2.1 Coupling Capacitors
          2. 9.14.1.2.2 Polarity Inversion
          3. 9.14.1.2.3 Lane Reversal
        3. 9.14.1.3 Non-Standard PCIe Connections
          1. 9.14.1.3.1 PCB Stackup Specifications
          2. 9.14.1.3.2 Routing Specifications
      2. 9.14.2 PCIe Peripheral Register Descriptions
      3. 9.14.3 PCIe Electrical Data and Timing
    15. 9.15 Real-Time Clock (RTC)
      1. 9.15.1 RTC Register Descriptions
    16. 9.16 Secure Digital and Secure Digital Input Output (SD and SDIO)
      1. 9.16.1 SD and SDIO Peripheral Register Descriptions
      2. 9.16.2 SD and SDIO Electrical Data and Timing
        1. 9.16.2.1 SD Identification and Standard SD Mode
        2. 9.16.2.2 High-Speed SD Mode
    17. 9.17 Serial ATA Controller (SATA)
      1. 9.17.1 SATA Interface Design Specifications
        1. 9.17.1.1 SATA Interface Schematic
        2. 9.17.1.2 Compatible SATA Components and Modes
        3. 9.17.1.3 PCB Stackup Specifications
        4. 9.17.1.4 Routing Specifications
        5. 9.17.1.5 Coupling Capacitors
      2. 9.17.2 SATA Peripheral Register Descriptions
    18. 9.18 Serial Peripheral Interface (SPI)
      1. 9.18.1 SPI Peripheral Register Descriptions
      2. 9.18.2 SPI Electrical Data and Timing
    19. 9.19 Timers
      1. 9.19.1 Timer Peripheral Register Descriptions
      2. 9.19.2 Timer Electrical Data and Timing
    20. 9.20 Universal Asynchronous Receiver and Transmitter (UART)
      1. 9.20.1 UART Peripheral Register Descriptions
      2. 9.20.2 UART Electrical Data and Timing
    21. 9.21 Universal Serial Bus (USB2.0)
      1. 9.21.1 USB2.0 Peripheral Register Descriptions
      2. 9.21.2 USB2.0 Electrical Data and Timing
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
      2. 10.1.2 Device Speed Range Overview
    2. 10.2 Documentation Support
    3. 10.3 Related Links
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CYG|1031
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings (Unless Otherwise Noted)(1)(2)

MIN MAX UNIT
Steady State Supply voltage ranges: USB PHYs, 0.9 V (VDD_USB_0P9) -0.3 1.35 V
Core (CVDD, CVDDC, VDDT_SATA, VDDT_PCIE, VDDA_HDMI, VDDA_HD_1P0, VDDA_SD_1P0) -0.3 1.2 V
IO, 1.5 V (VDDA_PLL, VDDR_SATA, VDDR_PCIE, DVDD_DDR0, DVDD_DDR1)(3) -0.3 2.45 V
IO, 1.8 V (DVDD1P8, DEVOSC_DVDD18, VDD_USB0_1P8, VDD_USB1_1P8, VDDA_REF_1P8, VDDA_HD_1P8, VDDA_SD_1P8, DVDD_DDR0, DVDD_DDR1)(3) -0.3 2.45 V
IO, 3.3 V (DVDD_3P3, VDD_USB0_3P3, VDD_USB1_3P3) 0 3.8 V
Input and Output voltage ranges: V IO, 1.5-V pins -0.3
-0.3 		2.45
DVDD_DDRx + 0.3(3)		 V
V IO, 1.8-V pins -0.3
-0.3
-0.3 		2.45
DVDD1P8 + 0.3
DVDD_DDRx + 0.3(3)		 V
V IO, 3.3-V pins
(Steady State)		 -0.3
-0.3 		3.8
DVDD_3P3 + 0.3		 V
V IO, 3.3-V pins
(Transient Overshoot and Undershoot)		 20% of DVDD_3P3 for up to 20% of the signal period V
Operating junction temperature range, TJ:(4) (default) 0 95 °C
extended temperature -40 105
Storage temperature range, Tstg: (Default) -55 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
(3) For supply voltage pins, DVDD_DDRx:
  • 1.5 V is used for DDR3 SDRAM.
  • 1.8 V is used for DDR2 SDRAM.
(4) A heat dissipation solution is required for proper device operation. Thermal performance of the overall system must be carefully considered to ensure conformance with the recommended operating conditions. Heat generated by this device must be removed with the help of heat sinks, heat spreaders, or airflow. SmartReflex can significantly lower the power consumption of this device and its use is required for proper device operation. A thermal model can be provided for thermal simulation to estimate the system thermal environment. Contact your local TI representative for availability.

5.2 ESD Ratings

VALUE UNIT
ESD stress voltage, VESD:(1) HBM (Human Body Model)(2) ±1000 V
CDM (Charged-Device Model)(3) ±250 V
(1) Electrostatic discharge (ESD) to measure device sensitivity or immunity to damage caused by electrostatic discharges into the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if necessary precautions are taken. Pins listed as 1000 V may actually have higher performance.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.

5.3 Recommended Operating Conditions

MIN NOM MAX UNIT
CVDD Supply voltage, Variable Core, Adaptive Voltage Scaling (CVDD)(1) Initial Startup VINITnom × 0.95 1.00 or 1.05(7) VINITnom × 1.05 V
CYGA2 & CYG4 SRnom(8) × 0.95 0.85 - 1.00 SRnom × 1.05
CYG & CYG2 SRnom × 0.95 0.85-1.05(9) SRnom × 1.05
CVDDC Supply voltage, Constant Core (CVDDC, VDDT_SATA, VDDT_PCIE, VDDA_HDMI, VDDA_HD_1P0, VDDA_SD_1P0) 0.95 1 1.05 V
DVDD Supply voltage, IO, 3.3 V (DVDD_3P3, VDD_USB0_3P3, VDD_USB1_3P3)
(except I2C pins)		 3.13 3.3 3.47 V
Supply voltage, IO, I2C (DVDD_3P3) 3.13 3.3 3.47 V
Supply voltage, IO, 1.8 V (DVDD1P8, DEVOSC_DVDD18, VDD_USB0_1P8, VDD_USB1_1P8, VDDA_REF_1P8, VDDA_HD_1P8, VDDA_SD_1P8, DVDD_DDR0, DVDD_DDR1)(2) 1.71 1.8 1.89 V
Supply voltage, IO, 1.5 V (VDDA_PLL, VDDR_SATA, VDDR_PCIE, DVDD_DDR0, DVDD_DDR1)(2) 1.43 1.5 1.58 V
Supply voltage, IO, 0.9 V (VDD_USB_0P9) 0.85 0.9 0.95 V
VSS Supply ground (VSS, VSSA_PLL, VSSA_HD, VSSA_SD, VSSA_REF_1P8, DEVOSC_VSS)(3) 0 0 0 V
DDR_VREF DDR2 and DDR3 reference voltage(4) 0.48DVDD_DDRx 0.5DVDD_DDRx 0.52DVDD_DDRx V
VIH High-level input voltage, 3.3 V (except I2C pins) 2 V
High-level input voltage, I2C 0.7DVDD_3P3
High-level input voltage, 1.8 V 0.65DVDD1P8
VIL Low-level input voltage, 3.3 V (except I2C pins) 0.8 V
Low-level input voltage, I2C 0.3DVDD_3P3
Low-level input voltage, 1.8 V 0.35DVDD1P8
IOH High-level output current 6-mA IO buffers -6 mA
DDR[0], DDR[1] buffers @ 50-Ω impedance setting -8
IOL Low-level output current 6-mA IO buffers 6 mA
DDR[0], DDR[1] buffers @ 50-Ω impedance setting 8
VID Differential input voltage (SERDES_CLKN and SERDES_CLKP), [AC coupled] 0.25 2.0 V
tt Transition time, 10%-90%, All Inputs (unless otherwise specified in the electrical data sections) Lesser of 0.25P or 10(5) ns
TJ Operating junction temperature range(6) 0 95 °C
Extended operating junction temperature range -40 105
(1) This device supports, and requires the use of, SmartReflex technology with Adaptive Voltage Scaling based on die temperature and performance. The SmartReflex codes output from the device correspond to up to 32 linear voltage steps within the specified voltage range (32 steps is the recommended software upper limit and is not constrained by the silicon design), with the option to use fewer steps if desired, with a minimum of eight steps. TI requires that users design a supply that can handle multiple voltage steps within this range with ± 5% tolerances. Not incorporating a flexible supply may limit the system's ability to use the power saving capabilities of the SmartReflex technology. TI recommends using a fault-tolerant power supply design to protect against over-current conditions. For more details about adaptive voltage scaling for this device, see the AVS FAQ. For AVS disable data to aid in design of robust power supplies that may withstand momentary AVS control failure, see the device Power Estimation Spreadsheet (literature number SPRABK3).
(2) For supply voltage pins, DVDD_DDRx:
  • 1.5 V is used for DDR3 SDRAM.
  • 1.8 V is used for DDR2 SDRAM.
(3) Oscillator ground (DEVOSC_VSS) must be kept separate from other grounds and connected directly to the crystal load capacitor ground.
(4) DDR_VREF is expected to equal 0.5DVDD_DDRx of the transmitting device and to track variations in the DVDD_DDRx.
(5) P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input signals.
(6) A heat dissipation solution is required for proper device operation. Thermal performance of the overall system must be carefully considered to ensure conformance with the recommended operating conditions. Heat generated by this device must be removed with the help of heat sinks, heat spreaders, or airflow. SmartReflex can significantly lower the power consumption of this device and its use is required for proper device operation. A thermal model can be provided for thermal simulation to estimate the system thermal environment. Contact your local TI representative for availability.
(7) The initial CVDD voltage at power on must be 1.00V nominal (for CYGA2 and CYG4 devices) or 1.05V nominal (for CYG and CYG2 devices) and it must transition to the AVS target value adjusted by a AVS driver. This is required to maintain full power functionality and reliability targets specified by TI.
(8) SRnom refers to the unique SmartReflex core supply voltage set from the factory for each individual device.
(9) Upper range limit of 1.10 nominal value allowed.

Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)

PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
VOH Low and full speed: USB_DN and USB_DP 2.8 VDD_USBx_3P3 V
High speed: USB_DN and USB_DP 360 440 mV
High-level output voltage (3.3-V IO) DVDD_3P3 = MIN, IOH = MAX 2.4 V
VOL Low and full speed: USB_DN and USB_DP 0.0 0.3 V
High speed: USB_DN and USB_DP -10 10 mV
Low-level output voltage (3.3-V IO except I2C pins) DVDD_3P3 = MIN, IOL = MAX 0.4 V
Low-level output voltage
(3.3-V IO I2C pins)		 IO = 3 mA 0.4 V
II(3) Input current [DC]
(except I2C pins)		 VI = VSS to DVDD_3P3 without opposing internal resistor ±1 µA
VI = VSS to DVDD_3P3 with opposing internal pullup resistor(4) 100 µA
VI = VSS to DVDD_3P3 with opposing internal pulldown resistor(4) -100 µA
Input current [DC] (I2C) VI = VSS to DVDD_3P3 ±20 µA
IOZ(5) IO Off-state output current VO = DVDD_3P3 or VSS; internal pull disabled ±5 µA
VO = DVDD_3P3 or VSS; internal pull enabled ±100 µA
ICDD
  • Case Temp = 60ºC
  • ARM at 1.2 GHz, 75% utilization
  • DSP at 1 GHz, 25% utilization
  • HDVICP2-0 at 600 MHz, 1-ch 1080p60 encode
  • HDVICP2-1 at 600 MHz, 1-ch 1080p60 decode
  • HDMI display
  • SGX530 at 150 MHz, 15 fps
  • EMIF0 and EMIF1 at 800 MHz, 4480 MBps
  • USB 1x, EMAC 1x, SATA
 mA
Constant Core (CVDDC) supply current(6) 1491(2)
Variable Core (CVDD) supply current(6) 6463(2)
IDDD
  • Case Temp = 60ºC
  • ARM at 1.2 GHz, 75% utilization
  • DSP at 1 GHz, 25% utilization
  • HDVICP2-0 at 600 MHz, 1-ch 1080p60 encode
  • HDVICP2-1 at 600 MHz, 1-ch 1080p60 decode
  • HDMI display
  • SGX530 at 150 MHz, 15 fps
  • EMIF0 and EMIF1 at 800 MHz, 4480 MBps
  • USB 1x, EMAC 1x, SATA
 mA
3.3-V IO (DVDD_3P3, USB_VDDA3P3) supply current(6) 19(2)
1.8-V IO (DVDD1P8, DVDD_DDRx) supply current(6)(7) 11(2)
1.5-V IO (DVDD_DDRx) supply current(6)(7) 1241(2)
CI Input capacitance 2.8 pF
Co Output capacitance 2.8 pF
(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
(2) The ICDD and IDDD TYP power values shown in this table correspond to device speed grade 2 (CYG2).
(3) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II indicates the input leakage current and off-state (Hi-Z) output leakage current.
(4) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(5) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
(6) The actual current draw varies across manufacturing processes and is highly application-dependent. For use-case specific power estimates, see the device Power Estimation Spreadsheet (literature number SPRABK3).
(7) For supply voltage pins, DVDD_DDRx:
  • 1.5 V is used for DDR3 SDRAM.
  • 1.8 V is used for DDR2 SDRAM.

5.4 Thermal Resistance Characteristics

Table 5-1 Thermal Resistance Characteristics (PBGA Package) [CYG]

NO. °C/W(1)
1 RΘJC Junction-to-case 0.21
2 RΘJB Junction-to-board 3.93
(1) For proper device operation, a heatsink is required.