SPRSP61C October   2021  – December 2023 TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038C-Q1 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
        1. 5.4.1.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption
      2. 6.5.2 System Current Consumption - VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Current Consumption Graphs
      5. 6.5.5 Reducing Current Consumption
        1. 6.5.5.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics for PZ Package
    8. 6.8  Thermal Resistance Characteristics for PN Package
    9. 6.9  Thermal Resistance Characteristics for PM Package
    10. 6.10 Thermal Resistance Characteristics for PT Package
    11. 6.11 Thermal Design Considerations
    12. 6.12 System
      1. 6.12.1 Power Management Module (PMM)
        1. 6.12.1.1 Introduction
        2. 6.12.1.2 Overview
          1. 6.12.1.2.1 Power Rail Monitors
            1. 6.12.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.12.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.12.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.12.1.2.2 External Supervisor Usage
          3. 6.12.1.2.3 Delay Blocks
          4. 6.12.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.12.1.2.5 VREGENZ
        3. 6.12.1.3 External Components
          1. 6.12.1.3.1 Decoupling Capacitors
            1. 6.12.1.3.1.1 VDDIO Decoupling
            2. 6.12.1.3.1.2 VDD Decoupling
        4. 6.12.1.4 Power Sequencing
          1. 6.12.1.4.1 Supply Pins Ganging
          2. 6.12.1.4.2 Signal Pins Power Sequence
          3. 6.12.1.4.3 Supply Pins Power Sequence
            1. 6.12.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.12.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.12.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.12.1.4.3.4 Supply Slew Rate
        5. 6.12.1.5 Power Management Module Electrical Data and Timing
          1. 6.12.1.5.1 Power Management Module Operating Conditions
          2. 6.12.1.5.2 Power Management Module Characteristics
          3.        Supply Voltages
      2. 6.12.2 Reset Timing
        1. 6.12.2.1 Reset Sources
        2. 6.12.2.2 Reset Electrical Data and Timing
          1. 6.12.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.12.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.12.2.2.3 Reset Timing Diagrams
      3. 6.12.3 Clock Specifications
        1. 6.12.3.1 Clock Sources
        2. 6.12.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.12.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.12.3.2.1.1 Input Clock Frequency
            2. 6.12.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.12.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.12.3.2.1.4 X1 Timing Requirements
            5. 6.12.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.12.3.2.1.6 APLL Characteristics
            7. 6.12.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.12.3.2.1.8 Internal Clock Frequencies
        3. 6.12.3.3 Input Clocks and PLLs
        4. 6.12.3.4 XTAL Oscillator
          1. 6.12.3.4.1 Introduction
          2. 6.12.3.4.2 Overview
            1. 6.12.3.4.2.1 Electrical Oscillator
              1. 6.12.3.4.2.1.1 Modes of Operation
                1. 6.12.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.12.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.12.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.12.3.4.2.2 Quartz Crystal
            3. 6.12.3.4.2.3 GPIO Modes of Operation
          3. 6.12.3.4.3 Functional Operation
            1. 6.12.3.4.3.1 ESR – Effective Series Resistance
            2. 6.12.3.4.3.2 Rneg – Negative Resistance
            3. 6.12.3.4.3.3 Start-up Time
              1. 6.12.3.4.3.3.1 X1/X2 Precondition
            4. 6.12.3.4.3.4 DL – Drive Level
          4. 6.12.3.4.4 How to Choose a Crystal
          5. 6.12.3.4.5 Testing
          6. 6.12.3.4.6 Common Problems and Debug Tips
          7. 6.12.3.4.7 Crystal Oscillator Specifications
            1. 6.12.3.4.7.1 Crystal Oscillator Parameters
            2. 6.12.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.12.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.12.3.5 Internal Oscillators
          1. 6.12.3.5.1 INTOSC Characteristics
      4. 6.12.4 Flash Parameters
        1. 6.12.4.1 Flash Parameters 
      5. 6.12.5 RAM and ROM Parameters
      6. 6.12.6 Emulation/JTAG
        1. 6.12.6.1 JTAG Electrical Data and Timing
          1. 6.12.6.1.1 JTAG Timing Requirements
          2. 6.12.6.1.2 JTAG Switching Characteristics
          3. 6.12.6.1.3 JTAG Timing Diagram
        2. 6.12.6.2 cJTAG Electrical Data and Timing
          1. 6.12.6.2.1 cJTAG Timing Requirements
          2. 6.12.6.2.2 cJTAG Switching Characteristics
          3. 6.12.6.2.3 cJTAG Timing Diagram
      7. 6.12.7 GPIO Electrical Data and Timing
        1. 6.12.7.1 GPIO – Output Timing
          1. 6.12.7.1.1 General-Purpose Output Switching Characteristics
          2. 6.12.7.1.2 General-Purpose Output Timing Diagram
        2. 6.12.7.2 GPIO – Input Timing
          1. 6.12.7.2.1 General-Purpose Input Timing Requirements
          2. 6.12.7.2.2 Sampling Mode
        3. 6.12.7.3 Sampling Window Width for Input Signals
      8. 6.12.8 Interrupts
        1. 6.12.8.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.12.8.1.1 External Interrupt Timing Requirements
          2. 6.12.8.1.2 External Interrupt Switching Characteristics
          3. 6.12.8.1.3 External Interrupt Timing
      9. 6.12.9 Low-Power Modes
        1. 6.12.9.1 Clock-Gating Low-Power Modes
        2. 6.12.9.2 Low-Power Mode Wake-up Timing
          1. 6.12.9.2.1 IDLE Mode Timing Requirements
          2. 6.12.9.2.2 IDLE Mode Switching Characteristics
          3. 6.12.9.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.12.9.2.4 STANDBY Mode Timing Requirements
          5. 6.12.9.2.5 STANDBY Mode Switching Characteristics
          6. 6.12.9.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.12.9.2.7 HALT Mode Timing Requirements
          8. 6.12.9.2.8 HALT Mode Switching Characteristics
          9. 6.12.9.2.9 HALT Entry and Exit Timing Diagram
    13. 6.13 Analog Peripherals
      1. 6.13.1 Analog Pins and Internal Connections
      2. 6.13.2 Analog Signal Descriptions
      3. 6.13.3 Analog-to-Digital Converter (ADC)
        1. 6.13.3.1 ADC Configurability
          1. 6.13.3.1.1 Signal Mode
        2. 6.13.3.2 ADC Electrical Data and Timing
          1. 6.13.3.2.1 ADC Operating Conditions
          2. 6.13.3.2.2 ADC Characteristics
          3. 6.13.3.2.3 ADC Input Model
          4. 6.13.3.2.4 ADC Timing Diagrams
      4. 6.13.4 Temperature Sensor
        1. 6.13.4.1 Temperature Sensor Electrical Data and Timing
          1. 6.13.4.1.1 Temperature Sensor Characteristics
      5. 6.13.5 Comparator Subsystem (CMPSS)
        1. 6.13.5.1 CMPSS Connectivity Diagram
        2. 6.13.5.2 Block Diagram
        3. 6.13.5.3 CMPSS Electrical Data and Timing
          1. 6.13.5.3.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.13.5.3.2 CMPSS DAC Static Electrical Characteristics
          4. 6.13.5.3.3 CMPSS Illustrative Graphs
          5. 6.13.5.3.4 CMPSS DAC Dynamic Error
      6. 6.13.6 Buffered Digital-to-Analog Converter (DAC)
        1. 6.13.6.1 Buffered DAC Electrical Data and Timing
          1. 6.13.6.1.1 Buffered DAC Operating Conditions
          2. 6.13.6.1.2 Buffered DAC Electrical Characteristics
    14. 6.14 Control Peripherals
      1. 6.14.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.14.1.1 ePWM Electrical Data and Timing
          1. 6.14.1.1.1 ePWM Timing Requirements
          2. 6.14.1.1.2 ePWM Switching Characteristics
          3. 6.14.1.1.3 Trip-Zone Input Timing
            1. 6.14.1.1.3.1 Trip-Zone Input Timing Requirements
            2. 6.14.1.1.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.14.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.14.2.1 HRPWM Electrical Data and Timing
          1. 6.14.2.1.1 High-Resolution PWM Characteristics
      3. 6.14.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.14.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.14.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.14.4 Enhanced Capture (eCAP)
        1. 6.14.4.1 eCAP and HRCAP Block Diagram
        2. 6.14.4.2 eCAP Synchronization
        3. 6.14.4.3 eCAP Electrical Data and Timing
          1. 6.14.4.3.1 eCAP Timing Requirements
          2. 6.14.4.3.2 eCAP Switching Characteristics
      5. 6.14.5 High-Resolution Capture (HRCAP)
        1. 6.14.5.1 eCAP and HRCAP Block Diagram
        2. 6.14.5.2 HRCAP Electrical Data and Timing
          1. 6.14.5.2.1 HRCAP Switching Characteristics
          2. 6.14.5.2.2 HRCAP Figure and Graph
      6. 6.14.6 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.14.6.1 eQEP Electrical Data and Timing
          1. 6.14.6.1.1 eQEP Timing Requirements
          2. 6.14.6.1.2 eQEP Switching Characteristics
      7. 6.14.7 Sigma-Delta Filter Module (SDFM)
        1. 6.14.7.1 SDFM Electrical Data and Timing
          1. 6.14.7.1.1 SDFM Timing Requirements When Using Asynchronous GPIO - ASYNC - Option
    15. 6.15 Communications Peripherals
      1. 6.15.1 Controller Area Network (CAN)
      2. 6.15.2 Modular Controller Area Network (MCAN)
      3. 6.15.3 Inter-Integrated Circuit (I2C)
        1. 6.15.3.1 I2C Electrical Data and Timing
          1. 6.15.3.1.1 I2C Timing Requirements
          2. 6.15.3.1.2 I2C Switching Characteristics
          3. 6.15.3.1.3 I2C Timing Diagram
      4. 6.15.4 Power Management Bus (PMBus) Interface
        1. 6.15.4.1 PMBus Electrical Data and Timing
          1. 6.15.4.1.1 PMBus Electrical Characteristics
          2. 6.15.4.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.15.4.1.3 PMBus Standard Mode Switching Characteristics
      5. 6.15.5 Serial Communications Interface (SCI)
      6. 6.15.6 Serial Peripheral Interface (SPI)
        1. 6.15.6.1 SPI Master Mode Timings
          1. 6.15.6.1.1 SPI Master Mode Timing Requirements
          2. 6.15.6.1.2 SPI Master Mode Switching Characteristics - Clock Phase  0
          3. 6.15.6.1.3 SPI Master Mode Switching Characteristics - Clock Phase  1
          4. 6.15.6.1.4 SPI Master Mode Timing Diagrams
        2. 6.15.6.2 SPI Slave Mode Timings
          1. 6.15.6.2.1 SPI Slave Mode Timing Requirements
          2. 6.15.6.2.2 SPI Slave Mode Switching Characteristics
          3. 6.15.6.2.3 SPI Slave Mode Timing Diagrams
      7. 6.15.7 Local Interconnect Network (LIN)
      8. 6.15.8 Fast Serial Interface (FSI)
        1. 6.15.8.1 FSI Transmitter
          1. 6.15.8.1.1 FSITX Electrical Data and Timing
            1. 6.15.8.1.1.1 FSITX Switching Characteristics
            2. 6.15.8.1.1.2 FSITX Timings
        2. 6.15.8.2 FSI Receiver
          1. 6.15.8.2.1 FSIRX Electrical Data and Timing
            1. 6.15.8.2.1.1 FSIRX Timing Requirements
            2. 6.15.8.2.1.2 FSIRX Switching Characteristics
            3. 6.15.8.2.1.3 FSIRX Timings
        3. 6.15.8.3 FSI SPI Compatibility Mode
          1. 6.15.8.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.15.8.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.15.8.3.1.2 FSITX SPI Signaling Mode Timings
      9. 6.15.9 Host Interface Controller (HIC)
        1. 6.15.9.1 HIC Electrical Data and Timing
          1. 6.15.9.1.1 HIC Timing Requirements
          2. 6.15.9.1.2 HIC Switching Characteristics
          3. 6.15.9.1.3 HIC Timing Diagrams
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
        3. 7.3.1.3 Global Shared RAM (GSx RAM)
        4. 7.3.1.4 Message RAM
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit (FPU)
      2. 7.6.2 Fast Integer Division Unit
      3. 7.6.3 Trigonometric Math Unit (TMU)
      4. 7.6.4 VCRC Unit
    7. 7.7  Control Law Accelerator (CLA)
    8. 7.8  Embedded Real-Time Analysis and Diagnostic (ERAD)
    9. 7.9  Background CRC-32 (BGCRC)
    10. 7.10 Direct Memory Access (DMA)
    11. 7.11 Device Boot Modes
      1. 7.11.1 Device Boot Configurations
        1. 7.11.1.1 Configuring Boot Mode Pins
        2. 7.11.1.2 Configuring Boot Mode Table Options
      2. 7.11.2 GPIO Assignments
    12. 7.12 Security
      1. 7.12.1 Securing the Boundary of the Chip
        1. 7.12.1.1 JTAGLOCK
        2. 7.12.1.2 Zero-pin Boot
      2. 7.12.2 Dual-Zone Security
      3. 7.12.3 Disclaimer
    13. 7.13 Watchdog
    14. 7.14 C28x Timers
    15. 7.15 Dual-Clock Comparator (DCC)
      1. 7.15.1 Features
      2. 7.15.2 Mapping of DCCx Clock Source Inputs
    16. 7.16 Configurable Logic Block (CLB)
    17. 7.17 Functional Safety
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Applications and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 Automotive Pump
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Automotive Pump Resources
        2. 8.3.1.2 Automotive HVAC Compressor
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 HVAC Resources
        3. 8.3.1.3 On-Board Charger (OBC)
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 OBC Resources
        4. 8.3.1.4 Servo Drive Control Module
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 Servo Drive Control Module Resources
        5. 8.3.1.5 Solar Micro Inverter
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 Solar Micro Inverter Resources
        6. 8.3.1.6 Merchant Telecom Rectifiers
          1. 8.3.1.6.1 System Block Diagram
          2. 8.3.1.6.2 Merchant Telecom Rectifiers Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3.1 Analog Signals

Table 5-2 Analog Signals
SIGNAL NAME PIN TYPE DESCRIPTION 100 PZ 80 PN 64 PMQ 64 PM 48 PT
A0 I ADC-A Input 0 23 19 15 15 11
A1 I ADC-A Input 1 22 18 14 14 10
A2 I ADC-A Input 2 17 13 9 9 6
A3 I ADC-A Input 3 18 12 8 8 5
A4 I ADC-A Input 4 36 27 23 23 19
A5 I ADC-A Input 5 35 17 13 13 9
A6 I ADC-A Input 6 14 10 6 6 4
A7 I ADC-A Input 7 31 23 19 19 15
A8 I ADC-A Input 8 37 24 20 20 16
A9 I ADC-A Input 9 38 28 24 24 20
A10 I ADC-A Input 10 40 29 25 25 21
A11 I ADC-A Input 11 20 16 12 12 8
A12 I ADC-A Input 12 28 22 18 18 14
A14 I ADC-A Input 14 19 15 11 11
A15 I ADC-A Input 15 14 10 10 7
AIO224 I Analog Pin Used For Digital Input 224 17 13 9 9 6
AIO225 I Analog Pin Used For Digital Input 225 36 27 23 23 19
AIO226 I Analog Pin Used For Digital Input 226 15 11 7 7 4
AIO227 I Analog Pin Used For Digital Input 227 38 28 24 24 20
AIO228 I Analog Pin Used For Digital Input 228 14 10 6 6 4
AIO229 I Analog Pin Used For Digital Input 229 18
AIO230 I Analog Pin Used For Digital Input 230 40 29 25 25 21
AIO231 I Analog Pin Used For Digital Input 231 23 19 15 15 11
AIO232 I Analog Pin Used For Digital Input 232 22 18 14 14 10
AIO233 I Analog Pin Used For Digital Input 233 14 10 10 7
AIO236 I Analog Pin Used For Digital Input 236 39 28 24 24 20
AIO237 I Analog Pin Used For Digital Input 237 20 16 12 12 8
AIO238 I Analog Pin Used For Digital Input 238 28 22 18 18 14
AIO239 I Analog Pin Used For Digital Input 239 19 15 11 11
AIO240 I Analog Pin Used For Digital Input 240 37
AIO241 I Analog Pin Used For Digital Input 241 24 20 20 16
AIO242 I Analog Pin Used For Digital Input 242 16 12 8 8 5
AIO244 I Analog Pin Used For Digital Input 244 21 17 13 13 9
AIO245 I Analog Pin Used For Digital Input 245 31 23 19 19 15
AIO247 I Analog Pin Used For Digital Input 247 42
AIO248 I Analog Pin Used For Digital Input 248 29 22 18 18 14
AIO249 I Analog Pin Used For Digital Input 249 35
AIO251 I Analog Pin Used For Digital Input 251 30
AIO252 I Analog Pin Used For Digital Input 252 32
AIO253 I Analog Pin Used For Digital Input 253 41
B0 I ADC-B Input 0 41 24 20 20 16
B1 I ADC-B Input 1 40 29 25 25 21
B2 I ADC-B Input 2 15 11 7 7 4
B3 I ADC-B Input 3 16 12 8 8 5
B4 I ADC-B Input 4 39 28 24 24 20
B5 I ADC-B Input 5 32, 48 33
B6 I ADC-B Input 6 17 13 9 9 6
B7 I ADC-B Input 7 22 18 14 14 10
B8 I ADC-B Input 8 36 27 23 23 19
B9 I ADC-B Input 9 18 14 10 10 7
B10 I ADC-B Input 10 20 16 12 12 8
B11 I ADC-B Input 11 30, 49 34
B12 I ADC-B Input 12 21 17 13 13 9
B14 I ADC-B Input 14 19 15 11 11
B15 I ADC-B Input 15 23 19 15 15 11
C0 I ADC-C Input 0 20 16 12 12 8
C1 I ADC-C Input 1 29 22 18 18 14
C2 I ADC-C Input 2 21 17 13 13 9
C3 I ADC-C Input 3 31 23 19 19 15
C4 I ADC-C Input 4 19 15 11 11
C5 I ADC-C Input 5 28 12 8 8 5
C6 I ADC-C Input 6 15 11 7 7 4
C7 I ADC-C Input 7 18 14 10 10 7
C8 I ADC-C Input 8 39 28 24 24 20
C9 I ADC-C Input 9 17 13 9 9 6
C10 I ADC-C Input 10 40 29 25 25 21
C11 I ADC-C Input 11 41 24 20 20 16
C14 I ADC-C Input 14 42 27 23 23 19
C15 I ADC-C Input 15 23 19 15 15 11
CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0 14 10 10 7
CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1 20 16 12 12 8
CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0 17 13 9 9 6
CMP1_HP1 I CMPSS-1 High Comparator Positive Input 1 20 16 12 12 8
CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2 14 10 6 6 4
CMP1_HP3 I CMPSS-1 High Comparator Positive Input 3 14 10 10 7
CMP1_HP4 I CMPSS-1 High Comparator Positive Input 4 22 18 14 14 10
CMP1_HP5 I CMPSS-1 High Comparator Positive Input 5 32, 48 33
CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0 14 10 10 7
CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1 20 16 12 12 8
CMP1_LP0 I CMPSS-1 Low Comparator Positive Input 0 17 13 9 9 6
CMP1_LP1 I CMPSS-1 Low Comparator Positive Input 1 20 16 12 12 8
CMP1_LP2 I CMPSS-1 Low Comparator Positive Input 2 14 10 6 6 4
CMP1_LP3 I CMPSS-1 Low Comparator Positive Input 3 14 10 10 7
CMP1_LP4 I CMPSS-1 Low Comparator Positive Input 4 22 18 14 14 10
CMP1_LP5 I CMPSS-1 Low Comparator Positive Input 5 32, 48 33
CMP2_HN0 I CMPSS-2 High Comparator Negative Input 0 40 29 25 25 21
CMP2_HN1 I CMPSS-2 High Comparator Negative Input 1 28 22 18 18 14
CMP2_HP0 I CMPSS-2 High Comparator Positive Input 0 36 27 23 23 19
CMP2_HP1 I CMPSS-2 High Comparator Positive Input 1 28 22 18 18 14
CMP2_HP2 I CMPSS-2 High Comparator Positive Input 2 38 28 24 24 20
CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3 40 29 25 25 21
CMP2_HP4 I CMPSS-2 High Comparator Positive Input 4 41 24 20 20 16
CMP2_HP5 I CMPSS-2 High Comparator Positive Input 5 35 17 13 13 9
CMP2_LN0 I CMPSS-2 Low Comparator Negative Input 0 40 29 25 25 21
CMP2_LN1 I CMPSS-2 Low Comparator Negative Input 1 28 22 18 18 14
CMP2_LP0 I CMPSS-2 Low Comparator Positive Input 0 36 27 23 23 19
CMP2_LP1 I CMPSS-2 Low Comparator Positive Input 1 28 22 18 18 14
CMP2_LP2 I CMPSS-2 Low Comparator Positive Input 2 38 28 24 24 20
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3 40 29 25 25 21
CMP2_LP4 I CMPSS-2 Low Comparator Positive Input 4 41 24 20 20 16
CMP2_LP5 I CMPSS-2 Low Comparator Positive Input 5 35 17 13 13 9
CMP3_HN0 I CMPSS-3 High Comparator Negative Input 0 16 12 8 8 5
CMP3_HN1 I CMPSS-3 High Comparator Negative Input 1 21 17 13 13 9
CMP3_HP0 I CMPSS-3 High Comparator Positive Input 0 15 11 7 7 4
CMP3_HP1 I CMPSS-3 High Comparator Positive Input 1 21 17 13 13 9
CMP3_HP2 I CMPSS-3 High Comparator Positive Input 2 23 19 15 15 11
CMP3_HP3 I CMPSS-3 High Comparator Positive Input 3 16 12 8 8 5
CMP3_HP4 I CMPSS-3 High Comparator Positive Input 4 19 15 11 11
CMP3_HP5 I CMPSS-3 High Comparator Positive Input 5 18 12 8 8 5
CMP3_LN0 I CMPSS-3 Low Comparator Negative Input 0 16 12 8 8 5
CMP3_LN1 I CMPSS-3 Low Comparator Negative Input 1 21 17 13 13 9
CMP3_LP0 I CMPSS-3 Low Comparator Positive Input 0 15 11 7 7 4
CMP3_LP1 I CMPSS-3 Low Comparator Positive Input 1 21 17 13 13 9
CMP3_LP2 I CMPSS-3 Low Comparator Positive Input 2 23 19 15 15 11
CMP3_LP3 I CMPSS-3 Low Comparator Positive Input 3 16 12 8 8 5
CMP3_LP4 I CMPSS-3 Low Comparator Positive Input 4 19 15 11 11
CMP3_LP5 I CMPSS-3 Low Comparator Positive Input 5 18 12 8 8 5
CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0 42 27 23 23 19
CMP4_HN1 I CMPSS-4 High Comparator Negative Input 1 31 23 19 19 15
CMP4_HP0 I CMPSS-4 High Comparator Positive Input 0 39 28 24 24 20
CMP4_HP1 I CMPSS-4 High Comparator Positive Input 1 31 23 19 19 15
CMP4_HP2 I CMPSS-4 High Comparator Positive Input 2 29 22 18 18 14
CMP4_HP3 I CMPSS-4 High Comparator Positive Input 3 42 27 23 23 19
CMP4_HP4 I CMPSS-4 High Comparator Positive Input 4 37 24 20 20 16
CMP4_HP5 I CMPSS-4 High Comparator Positive Input 5 30, 49 34
CMP4_LN0 I CMPSS-4 Low Comparator Negative Input 0 42 27 23 23 19
CMP4_LN1 I CMPSS-4 Low Comparator Negative Input 1 31 23 19 19 15
CMP4_LP0 I CMPSS-4 Low Comparator Positive Input 0 39 28 24 24 20
CMP4_LP1 I CMPSS-4 Low Comparator Positive Input 1 31 23 19 19 15
CMP4_LP2 I CMPSS-4 Low Comparator Positive Input 2 29 22 18 18 14
CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3 42 27 23 23 19
CMP4_LP4 I CMPSS-4 Low Comparator Positive Input 4 37 24 20 20 16
CMP4_LP5 I CMPSS-4 Low Comparator Positive Input 5 30, 49 34
DACA_OUT O Buffered DAC-A Output. 23 19 15 15 11
DACB_OUT O Buffered DAC-B Output. 22 18 14 14 10
VDAC I Optional external reference voltage for on-chip DACs. 16 12 8 8 5
VREFHI I ADC High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHI and VREFLO pins. 24, 25 20 16 16 12
VREFLO I ADC Low Reference 26, 27 21 17 17 13