SLOS660C January   2010  – October 2015 TPA2028D1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Operating Characteristics
    7. 7.7 I2C Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Automatic Gain Control
      2. 9.3.2 Operation With DACs and CODECs
      3. 9.3.3 Filter Free Operation and Ferrite Bead Filters
      4. 9.3.4 General I2C Operation
        1. 9.3.4.1 Single- and Multiple-Byte Transfers
        2. 9.3.4.2 Single-Byte Write
        3. 9.3.4.3 Multiple-Byte Write and Incremental Multiple-Byte Write
        4. 9.3.4.4 Single-Byte Read
        5. 9.3.4.5 Multiple-Byte Read
    4. 9.4 Device Functional Modes
      1. 9.4.1 Enable/Disable Amplifier
      2. 9.4.2 TPA2028D1 AGC and Start-Up Operation
        1. 9.4.2.1 AGC Startup Condition
      3. 9.4.3 Short Circuit Auto-Recovery
    5. 9.5 Programming
      1. 9.5.1 TPA2028D1 AGC Recommended Settings
    6. 9.6 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Decoupling Capacitor CS
        2. 10.2.2.2 Input Capacitors CI)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling Capacitors
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Component Placement
      2. 12.1.2 Trace Width
      3. 12.1.3 Pad Size
    2. 12.2 Layout Example
    3. 12.3 Efficiency and Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted).
MIN MAX UNIT
VDD Supply voltage PVDD –0.3 6 V
Input voltage EN, IN+, IN– –0.3 VDD+0.3 V
SDA, SCL –0.3 6 V
Continuous total power dissipation See Thermal Information
RLOAD Minimum load resistance 3.2 Ω
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD Supply voltage PVDD 2.5 5.5 V
VIH High-level input voltage EN, SDA, SCL 1.3 V
VIL Low-level input voltage EN, SDA, SCL 0.6 V
TA Operating free-air temperature –40 85 °C

7.4 Thermal Information

THERMAL METRIC(1) TPA2028D1 UNIT
YZF (DSBGA)
9 PINS
RθJA Junction-to-ambient thermal resistance 9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.7 °C/W
RθJB Junction-to-board thermal resistance 70 °C/W
ψJT Junction-to-top characterization parameter 3.3 °C/W
ψJB Junction-to-board characterization parameter 69.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

at TA = 25°C, VDD = 3.6 V, SDZ = 1.3 V, and RL = 8 Ω + 33 μH (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Supply voltage range 2.5 3.6 5.5 V
ISDZ Shutdown quiescent current EN = 0.35 V, VDD = 2.5 V 0.1 1 µA
EN = 0.35 V, VDD = 3.6 V 0.2 1
EN = 0.35 V, VDD = 5.5 V 0.3 1
ISWS Software shutdown quiescent current EN = 1.3 V, VDD = 2.5 V 35 50 µA
EN = 1.3 V, VDD = 3.6 V 50 70
EN = 1.3 V, VDD = 5.5 V 75 100
IDD Supply current VDD = 2.5 V 1.5 2.5 mA
VDD = 3.6 V 1.7 2.7
VDD = 5.5 V 2 3.5
fSW Class D Switching Frequency 275 300 325 kHz
IIH High-level input current VDD = 5.5 V, EN = 5.8 V 1 µA
IIL Low-level input current VDD = 5.5 V, EN = –0.3 V –1 µA
tSTART Start-up time 2.5 V ≤ VDD ≤ 5.5 V no pop, CIN ≤ 1 μF 5 ms
POR Power on reset ON threshold 2 2.3 V
POR Power on reset hysteresis 0.2 V
CMRR Input common mode rejection RL = 8 Ω, Vicm = 0.5 V and Vicm = VDD – 0.8 V,
differential inputs shorted		 –75 dB
Voo Output offset voltage VDD = 3.6 V, AV = 6 dB, RL = 8 Ω, inputs ac grounded 1.5 10 mV
ZOUT Output Impedance in shutdown mode EN = 0.35 V 2 kΩ
Gain accuracy Compression and limiter disabled, Gain = 0 to 30 dB –0.5 0.5 dB
PSRR Power supply rejection ratio VDD = 2.5 V to 4.7 V –80 dB

7.6 Operating Characteristics

at TA = 25°C, VDD = 3.6 V, EN = 1.3 V, RL = 8 Ω +33 μH, and AV = 6 dB (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
kSVR power-supply ripple rejection ratio VDD = 3.6 Vdc with ac of 200 mVPP at 217 Hz –70 dB
THD+N Total harmonic distortion + noise faud_in = 1 kHz; PO = 550 mW; VDD = 3.6 V 0.1%
faud_in = 1 kHz; PO = 1.25 W; VDD = 5 V 0.1%
faud_in = 1 kHz; PO = 710 mW; VDD = 3.6 V 1%
faud_in = 1 kHz; PO = 1.4 W; VDD = 5 V 1%
NfonF Output integrated noise Av = 6 dB 42 μV
NfoA Output integrated noise Av = 6 dB floor, A-weighted 30 μV
FR Frequency response Av = 6 dB 20 20000 Hz
Pomax Maximum output power THD+N = 10%, VDD = 5 V, RL = 8 Ω 1.72 W
THD+N = 10%, VDD = 3.6 V, RL = 8 Ω 880 mW
THD+N = 1%, VDD = 5 V, RL = 8 Ω 1.4 W
THD+N = 1% , VDD = 3.6 V, RL = 8 Ω 710 mW
THD+N = 1% , VDD = 5 V, RL = 4 Ω 2.5 W
THD+N = 10% , VDD = 5 V, RL = 4 Ω 3 W
η Efficiency THD+N = 1%, VDD = 3.6 V, RL = 8 Ω, PO= 0.71 W 91%
THD+N = 1%, VDD = 5 V, RL = 8 Ω, PO = 1.4 W 93%

7.7 I2C Timing Requirements

For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
MIN TYP MAX UNIT
fSCL Frequency, SCL No wait states 400 kHz
tW(H) Pulse duration, SCL high 0.6 μs
tW(L) Pulse duration, SCL low 1.3 μs
tSU(1) Setup time, SDA to SCL 100 ns
th1 Hold time, SCL to SDA 10 ns
t(buf) Bus free time between stop and start condition 1.3 μs
tSU2 Setup time, SCL to start condition 0.6 μs
th2 Hold time, start condition to SCL 0.6 μs
tSU3 Setup time, SCL to stop condition 0.6 μs
TPA2028D1 scl_tim_los492.gif Figure 1. SCL and SDA Timing
TPA2028D1 st_stop_los524.gif Figure 2. Start and Stop Conditions Timing

7.8 Typical Characteristics

with C(DECOUPLE) = 1 μF, CI = 1 µF. All THD + N graphs are taken with outputs out of phase (unless otherwise noted).
TPA2028D1 g001_slos660.gif
Figure 3. Quiescent Supply Current vs Supply Voltage
TPA2028D1 g003_slos660.gif
Figure 5. Output Level vs Input Level With Limiter Enabled
TPA2028D1 g005_slos660.gif
Figure 7. Output Level vs Input Level With 4:1 Compression
TPA2028D1 g007_slos660.gif
Figure 9. Output Level vs Input Level
TPA2028D1 g008_slos660.gif
Figure 11. Total Harmonic Distortion + Noise vs Frequency
TPA2028D1 g009_slos660.gif
Figure 13. Total Harmonic Distortion + Noise vs Frequency
TPA2028D1 g012_slos660.gif
Figure 15. Total Harmonic Distortion + Noise vs Output Power
TPA2028D1 g015_slos660.gif
Figure 17. Efficiency vs Output Power
TPA2028D1 g016_slos660.gif
Figure 19. Power Dissipation vs Output Power
TPA2028D1 g017_slos660.gif
Figure 21. Supply Current vs Output Power
TPA2028D1 g021_slos660.gif
Figure 23. Output Power vs Supply Voltage
TPA2028D1 sh_dn2_los660.gif
Figure 25. Shutdown Gain Ramp Comparison
TPA2028D1 g024_los660.gif
Figure 27. Startup Time
TPA2028D1 g002_slos660.gif
Figure 4. Supply Current vs Supply Voltage in Shutdown
TPA2028D1 g004_slos660.gif
Figure 6. Output Level vs Input Level With 2:1 Compression
TPA2028D1 g006_slos660.gif
Figure 8. Output Level vs Input Level With 8:1 Compression
TPA2028D1 g014_slos660.gif
Figure 10. Supply Ripple Rejection Ratio vs Frequency
TPA2028D1 g010_slos660.gif
Figure 12. Total Harmonic Distortion + Noise vs Frequency
TPA2028D1 g011_slos660.gif
Figure 14. Total Harmonic Distortion + Noise vs Frequency
TPA2028D1 g013_slos660.gif
Figure 16. Total Harmonic Distortion + Noise vs Output Power
TPA2028D1 g018_los592.gif
Figure 18. Efficiency vs Output Power
TPA2028D1 g019_slos660.gif
Figure 20. Power Dissipation vs Output Power
TPA2028D1 g020_slos660.gif
Figure 22. Supply Current vs Output Power
TPA2028D1 g022_slos660.gif
Figure 24. Output Power vs Supply Voltage
TPA2028D1 st_up2_los660.gif
Figure 26. Startup Gain Ramp Comparison
TPA2028D1 Z_gain_los660.gif
Figure 28. Nominal Input Impedance - Per Leg