SLOS759E March   2012  – December 2015 TPA3111D1-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Characteristics: VCC = 24 V
    6. 6.6 DC Characteristics: VCC = 12 V
    7. 6.7 AC Characteristics: VCC = 24 V
    8. 6.8 AC Characteristics: VCC = 12 V
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DC Detect
      2. 7.3.2 Short-Circuit Protection and Automatic Recovery Feature
      3. 7.3.3 Thermal Protection
      4. 7.3.4 GVDD Supply
    4. 7.4 Device Functional Modes
      1. 7.4.1 Gain Setting Through Gain0 and Gain1 Inputs
      2. 7.4.2 SD Operation
      3. 7.4.3 PLIMIT
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Class-D Operation
        2. 8.2.2.2  TPA3111D1-Q1 Modulation Scheme
        3. 8.2.2.3  Ferrite Bead Filter Considerations
        4. 8.2.2.4  Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
        5. 8.2.2.5  When to Use an Output Filter for EMI Suppression
        6. 8.2.2.6  Input Resistance
        7. 8.2.2.7  Input Capacitor, CI
        8. 8.2.2.8  BSN and BSP Capacitors
        9. 8.2.2.9  Differential Inputs
        10. 8.2.2.10 Using Low-ESR Capacitors
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PWP Package
28-Pin HSSOP With PowerPAD™
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
AGND 8 — Analog supply ground, connect to the thermal pad.
AVCC 7 P Analog supply
AVCC 14 P Connect AVCC supply to this pin
BSN 22, 26 I Bootstrap I/O for negative high-side FET
BSP 17, 21 I Bootstrap I/O for positive high-side FET
FAULT 2 O Open drain output used to display short circuit or DC-detect fault status. Voltage compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise both short circuit faults and DC-detect faults must be reset by cycling PVCC.
GAIN0 5 I Gain select least significant bit. TTL logic levels with compliance to AVCC.
GAIN1 6 I Gain select most significant bit. TTL logic levels with compliance to AVCC.
GND 3, 4 — Connect to local ground
GVDD 9 O High-side FET gate drive supply, nominal voltage is 7 V. This pin can also be used as supply for PLIMIT divider. Add a 1-μF capacitor to ground at this pin.
INN 11 I Negative audio input, biased at 3 V.
INP 12 I Positive audio input, biased at 3 V.
NC 13 — Not connected
OUTN 23, 25 O Class-D H-bridge negative output
OUTP 18, 20 O Class-D H-bridge positive output
PGND 19, 24 — Power ground for the H-bridges
PLIMIT 10 I Power limit level adjust. Connect directly to GVDD pin for no power limiting. Add a 1-μF capacitor to ground at this pin.
PVCC 15, 16, 27, 28 P Power supply for H-bridge. PVCC pins are also connected internally.
SD 1 I Shutdown logic input for audio amplifier (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC.