SLOS793B September   2012  – September 2015 TPA3112D1-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Characteristics
    6. 6.6 DC Characteristics
    7. 6.7 AC Characteristics
    8. 6.8 AC Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DC Detect
      2. 7.3.2 Short-Circuit Protection and Automatic Recovery Feature
      3. 7.3.3 Thermal Protection
      4. 7.3.4 GVDD Supply
    4. 7.4 Device Functional Modes
      1. 7.4.1 Gain Setting Through GAIN0 and GAIN1 Inputs
      2. 7.4.2 SD Operation
      3. 7.4.3 PLIMIT
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Class-D Operation
        2. 8.2.2.2  TPA3112D1-Q1 Modulation Scheme
        3. 8.2.2.3  Ferrite Bead Filter Considerations
        4. 8.2.2.4  Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
        5. 8.2.2.5  When to Use an Output Filter for EMI Suppression
        6. 8.2.2.6  Input Resistance
        7. 8.2.2.7  Input Capacitor, CI
        8. 8.2.2.8  BSN and BSP Capacitors
        9. 8.2.2.9  Differential Inputs
        10. 8.2.2.10 Using Low-ESR Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The TPA3112D1-Q1 can be used with a small, inexpensive ferrite bead output filter for most applications. However, since the Class-D switching edges are very fast, it is necessary to take care when planning the layout of the printed circuit board. The following suggestions help to meet EMC requirements.

  • Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC and AVCC terminals as possible. Large (220-μF or greater) bulk power supply decoupling capacitors should be placed near the TPA3112D1-Q1 on the PVCC supplies. Local, high-frequency bypass capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the thermal pad directly for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between 220 pF and 1000 pF and a larger mid-frequency cap of value between 0.1 mF and 1 mF also of good quality to the PVCC connections at each end of the chip.
  • Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to PGND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna.
  • Output filter—The ferrite EMI filter should be placed as close to the output terminals as possible for the best EMI performance. The LC filter should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be grounded to power ground.
  • Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35 mm. Seven rows of solid vias (three vias per row, 0.33 mm or 13 mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application Report SLMA002 for more information about using the TSSOP thermal pad.

For an example layout, see the TPA3112D1-Q1 Evaluation Module User's Guide, SLOU272. Both the EVM user's guide and the thermal pad application note are available on the TI website at http://www.ti.com.

10.2 Layout Example

TPA3112D1-Q1 layout_slos793.gif Figure 21. TPA3112D1-Q1 Layout Example for BTL Output