Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
This section describes a 2.1 master-and-slave application. The master is configured as stereo outputs and the slave is configured as a mono PBTL output.
|DESIGN PARAMETERS||EXAMPLE VALUE|
|Input voltage range, V(PVCC)||4.5 V to 26 V|
|PWM output frequencies||400 kHz, 500 kHz, 600 kHz, 1 MHz or 1.2 MHz|
|Maximum output power||50 W|
The TPA311xD2-Q1 family is a very flexible and easy-to-use class-D amplifier; therefore, the design process is straightforward. Before beginning the design, gather the following information regarding the audio system.
Set the PWM frequency by using AM0, AM1 and AM2 pins.
In order to select the amplifier gain setting, the designer must determine the maximum power target and the speaker impedance. Once these parameters have been determined, calculate the required output-voltage swing which delivers the maximum output power.
Choose the lowest analog gain setting that produces an output-voltage swing greater than the required output swing for maximum power. The analog gain and master or slave mode can be set by selecting the voltage divider resistors (R1 and R2) on the GAIN/SLV pin.
Select the bulk capacitors at the PVCC inputs for proper voltage margin and adequate capacitance to support the power requirements. In practice, with a well-designed power supply, two 100-μF, 50-V capacitors should be sufficient. One capacitor should be placed near the PVCC inputs at each side of the device. PVCC capacitors should be a low-ESR type because they are being used in a high-speed switching application.
Good-quality decoupling capacitors must be added at each of the PVCC inputs to provide good reliability, good audio performance, and to meet regulatory requirements. X5R or better ratings should be used in this application. Consider temperature, ripple current, and voltage overshoots when selecting decoupling capacitors. Also, these decoupling capacitors should be located near the PVCC and GND connections to the device in order to minimize series inductances.
Each of the outputs requires bootstrap capacitors to provide gate drive for the high-side output FETs. For this design, use 0.22-μF, 25-V capacitors of X5R quality or better.
|Gain = 26 dB||PVCC = 12 V||TA = 25°C|
|RL = 4 Ω||10-µH + 0.68-µF filter|
|Gain = 26 dB||PVCC = 14.4 V||TA = 25°C|
|RL = 4 Ω||10-µH + 0.68-µF filte|