SLVS639F October   2007  – February 2016 TPD12S521

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Circuit Protection Scheme
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Single-Chip ESD Solution for HDMI Driver
      2. 8.3.2 Supports All HDMI 1.3 and HDMI 1.4b Data Rates
      3. 8.3.3 Integrated Level Shifting for the Control Lines
      4. 8.3.4 ±8-kV Contact ESD Protection on External Lines
      5. 8.3.5 38-Pin TSSOP Provides Seamless Layout Option With HDMI Connector
      6. 8.3.6 Backdrive Protection
      7. 8.3.7 Lead-Free Package
      8. 8.3.8 On-Chip Current Regulator With 55-mA Current Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBT|38
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

  • The optimum placement is as close to the connector as possible.
    • EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures.
    • The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
  • Route the protected traces as straight as possible.
  • Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible.
    • Electric fields tend to build up on corners, increasing EMI coupling.

11.2 Layout Example

TPD12S521 Layout_new.gif
Use external and internal ground planes and stitch them together with VIAs as close to the GND pins of TPD12S521 as possible. This allows for a low impedance path to ground so that the device can properly dissipate an ESD event.