SLVSBC5D March   2012  – October 2015 TPD13S523


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEC 61000-4-2 Protection
      2. 7.3.2 Single-Chip ESD Solution
      3. 7.3.3 On-Chip 5-V Load Switch
      4. 7.3.4 Supports UTILITY Line Protection
      5. 7.3.5 < 0.05-pF Differential Capacitance Between TMDS Pairs
      6. 7.3.6 Industry Standard Package and Space-Saving Package
      7. 7.3.7 Supports Data Rates in Excess of 3.4 Gbps
      8. 7.3.8 RDYN = 0.5 Ω
      9. 7.3.9 Commercial Temperature Range
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 5V_SUPPLY Voltage Range
        2. Maximum HDMI Data Rate
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The TPD13S523 device offers little or no signal distortion during normal operation due to low I/O capacitance and ultra-low leakage current specifications. In the event of an ESD stress, this device ensures that the core circuitry is protected and the system is functioning properly. For proper operation, the following layout and design guidelines should be followed:

  1. Place the TPD13S523 as close to the connector as possible. This allows the TPD13S523 to remove the energy associated with ESD strike before it reaches the internal circuitry of the system board.
  2. Place two 0.1-μF capacitors very close to the 5V_SUPPLY and 5V_OUT pins. These capacitors will help limit the noise at the 5V_OUT power line, and also help with system level ESD protection.
  3. Ensure that there is enough metallization for the GND pad. During normal operation, the TPD13S523 ESD pins consume ultra-low leakage current. During the ESD event, GND pin will see multiple amps of current. A sufficient current path enables safe discharge of all the energy associated with the ESD strike.
  4. The critical routing paths for HDMI interface are the high-speed TMDS lines. With the PW package, all the TMDS lines (pin Dxx) can be routed in a single signal plane and still maintain the differential coupling and trace symmetry. This helps reduce the overall board manufacturing cost. The slow speed control lines can be routed in another signal layer through vias.
  5. If the UTILITY or any other pin is not utilizied, tie the pin to a ground rather than leave floating. Use a 75-Ω resistor to protect against shorts to ground.

10.2 Layout Examples

TPD13S523 TPD13S523_PW_layout.gif Figure 14. TPD13S523PWR Layout Example 13-Line HDMI Protection
TPD13S523 Layout_TPD13S523_RSV.gif Figure 15. TPD13S523RSVR Layout Example 13-Line HDMI Protection