SLVSBO7L December   2012  – January 2017 TPD1E05U06 , TPD4E05U06 , TPD6E05U06

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—JEDEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 ±15-kV IEC61000-4-2 Level 4 ESD Protection
      2. 7.3.2 IEC61000-4-4 EFT Protection
      3. 7.3.3 IEC61000-4-5 Surge Protection
      4. 7.3.4 I/O Capacitance
      5. 7.3.5 DC Breakdown Voltage
      6. 7.3.6 Ultra-Low Leakage Current
      7. 7.3.7 Low ESD Clamping Voltage
      8. 7.3.8 Industrial Temperature Range
      9. 7.3.9 Easy Flow-Through Routing
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 HDMI 2.0 Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Signal Range on Pin 1, 2, 4, or 5
        3. 8.2.1.3 Application Curves
      2. 8.2.2 HDMI 2.0 Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Signal Range
          2. 8.2.2.2.2 Operating Frequency
        3. 8.2.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 TPD4E05U06 Layout Example
      2. 10.2.2 TPD1E05U06 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings(1)(2)(3)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Electrical fast transient IEC 61000-4-4 (5/50 ns) 80 A
Peak pulse IEC 61000-4-5 Current (tp – 8/20 µs)(4) 2.5 A
IEC 61000-4-5 Power (tp – 8/20 µs)(4) 40 W
TA Operating temperature –40 125 °C
Tstg Storage temperature –65 155 °C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Absolute maximum ratings apply over recommended junction temperature range.
Voltages are with respect to GND unless otherwise noted.
Measured at 25°C.

ESD Ratings—JEDEC Specification

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±4000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±1500 V may actually have higher performance.

ESD Ratings—IEC Specification

VALUE UNIT
V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±12000 V
IEC 61000-4-2 air-gap discharge ±15000

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIO Input pin voltage 0 5.5 V
TA Operating free-air temperature –40 125 °C

Thermal Information

THERMAL METRIC(1) TPD1E05U06 TPD4E05U06 TPD6E05U06 UNIT
DPY (X1SON) DQA (USON) RVZ (USON)
2 PINS 10 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 697.3 327 197.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 471 189.5 119.1 °C/W
RθJB Junction-to-board thermal resistance 575.9 257.7 92.6 °C/W
ψJT Junction-to-top characterization parameter 175.7 60.9 22 °C/W
ψJB Junction-to-board characterization parameter 575.1 257 91.6 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 10 µA 5.5 V
VBR Break-down voltage IIO = 1 mA 6.5 8.5 V
Vclamp Clamp voltage I = 1 A, TLP, I/O to ground(1) 10 V
I = 5 A, TLP, I/O to ground(1) 14
I = 1 A, TLP, ground to I/O(1) 3
I = 5 A, TLP, ground to I/O(1) 7
ILEAK Leakage current VIO = 2.5 V 0.01 10 nA
RDYN DPY package dynamic resistance I/O to GND(2) 0.8 Ω
GND to I/O(2) 0.8
DQA package dynamic resistance I/O to GND(2) 0.8 Ω
GND to I/O(2) 0.8
RVZ package dynamic resistance I/O to GND(2) 0.8 Ω
GND to I/O(2) 0.8
Capacitance
CL Line capacitance(3) VIO = 2.5 V, f = 1 MHz,
I/O to GND
TPD1E05U06 DPY package 0.42 pF
TPD4E05U06 DQA package 0.5
TPD6E05U06 RVZ package 0.47
ΔCIO-TO-GND Variation of channel input capacitance GND Pin = 0 V, F = 1 GHz, VBIAS = 2.5 V, channel_x pin to GND – channel_y pin to GND 0.05 0.07 pF
CCROSS Channel to channel input capacitance GND Pin = 0 V, F = 1 GHz, VBIAS = 2.5 V, between channel pins 0.01 0.06 pF
Transmission Line Pulse (TLP) with 100 ns width, 200 ps rise time.
Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A.
Capacitance data is taken at 25°C.

Typical Characteristics

TPD1E05U06 TPD4E05U06 TPD6E05U06 C001_SLVSBO7.png
Figure 1. DC Voltage Sweep I-V Curve
TPD1E05U06 TPD4E05U06 TPD6E05U06 C003_SLVSBO7.png
Figure 3. Positive TLP Plot IO to GND
TPD1E05U06 TPD4E05U06 TPD6E05U06 C004_SLVSBO7.png
Figure 5. Leakage vs Temperature
TPD1E05U06 TPD4E05U06 TPD6E05U06 C006_SLVSBO7.png
Figure 7. –8-kV IEC Waveform
TPD1E05U06 TPD4E05U06 TPD6E05U06 C009_SLVSBO7.png
Figure 9. TPD4E05U06 Insertion Loss
TPD1E05U06 TPD4E05U06 TPD6E05U06 C002_SLVSBO7.png
Figure 2. Surge Curve (tp = 8/20 μs), Pin IO to GND
TPD1E05U06 TPD4E05U06 TPD6E05U06 C008_SLVSBO7.png
Figure 4. Negative TLP Plot IO to GND
TPD1E05U06 TPD4E05U06 TPD6E05U06 C005_SLVSBO7.png
Figure 6. 8-kV IEC Waveform
TPD1E05U06 TPD4E05U06 TPD6E05U06 C007_SLVSBO7.png
Figure 8. TPD1E05U06 Insertion Loss
TPD1E05U06 TPD4E05U06 TPD6E05U06 C010_SLVSBO7.png
Figure 10. TPD6E05U06 Insertion Loss