SLVSBQ9E December   2012  – October 2026 TPD4E1U06

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings—IEC Specification
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 IEC 61000-4-2 Level 4 ESD Protection
      2. 6.3.2 IEC 61000-4-5 Surge Protection
      3. 6.3.3 IEC 61000-4-4 EFT Protection
      4. 6.3.4 IO Capacitance
      5. 6.3.5 DC Breakdown Voltage
      6. 6.3.6 Ultra Low Leakage Current
      7. 6.3.7 Low ESD Clamping Voltage
      8. 6.3.8 Industrial Temperature Range
      9. 6.3.9 Small, Easy-to-Route Packages
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Signal Range on Pins 1, 3, 4, or 6
        2. 7.2.2.2 Operating Frequency
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Community Resources
    4. 8.4 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.6 Ultra Low Leakage Current

The I/O pins feature an ultra-low leakage current of 10nA (Maximum) with a bias of 2.5V.