SLVSI17 June   2025 TPD4S201-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings—JEDEC Specification
    3. 5.3 ESD Ratings—IEC Specification
    4. 5.4 ESD Ratings—ISO Specification
    5. 5.5 Recommended Operating Conditions
    6. 5.6 Thermal Information
    7. 5.7 Electrical Characteristics
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP, DM Pins): 28-VDC Tolerant
      2. 6.3.2 4-Channels of IEC 61000-4-2 ESD Protection (CC1, CC2, SBU1, SBU2 Pins)
      3. 6.3.3 CC1, CC2 Overvoltage Protection FETs 600-mA Capable for Passing VCONN Power
      4. 6.3.4 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VBIAS Capacitor Selection
        2. 7.2.2.2 CC Line Capacitance
        3. 7.2.2.3 FLT Pin Operation
        4. 7.2.2.4 Dead Battery Operation
        5. 7.2.2.5 Reference
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.1 VBIAS Capacitor Selection

As noted in the Section 5.5 table, a minimum of 50VBUS rated capacitor is required for the VBIAS pin, and a 50VBUS capacitor is recommended. The VBIAS capacitor is in parallel with the central diode clamp integrated inside the TPD4S201-Q1. A forward biased hiding diode connects the VBIAS pin to the C_CCx and C_SBUx pins. Therefore, when a short-to-VBUS event occurs at 20V, 20VBUS minus a forward biased diode drop is exposed to the VBIAS pin. Additionally, during the short-to-VBUS event, ringing almost doubles the settling voltage of 20V, allowing a potential 40V to be exposed to the C_CCx and C_SBUx pins. Therefore, at least a 50V capacitor is required to avoid the destruction of the VBIAS capacitor during short-to-VBUS events.

A 50V, X7R capacitor is recommended to further improve the derating performance of the capacitors. When the voltage across a real capacitor is increased, the capacitance value derates. The more the capacitor derates, the larger the ringing in the short-to-VBUS RLC circuit. The 50V X7R capacitors have great derating performance, allowing for the best short-to-VBUS performance of the TPD4S201-Q1.