SLIS170 December 2015 TPIC2010
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
TPIC2010 has nine channels of Actuator. Each channel is assigned to the most suitable DAC engine with a different type respectively. ACT(F/T/Ti) has 12-bit DAC. Upper 8 (MSB sign bit) are converted at a time in 5MHz and LSB 4 bits are output in sequence with 1.25-MHz PWM. SPIN, SLED and Load DAC has same DAC types and sampling rate with 312kHz. All channel (except SLED and STP) have x6 gain. The DAC for STP is 8-bits resolution output with 40 kHz PWM, no Feed Back. The Gain for STP is 5x relative to P5V voltage. Table 36 shows configuration of each actuator.
|Type||8-bit over sampling||8-bit over sampling||8-bit over sampling||8-bit over sampling||1 bit Direct Duty PWM|
|Sampling||1.25M / 10bit
312K / 12bit
|1.25M / 10bit
312K / 12bit
|PWM freq||312 kHz||78 kHz||156 kHz||312 kHz||40 kHz|
|Out range||±6 V||±440 mA||±6 V||±6 V||±(P5V*1)|
|Feed back||Voltage feedback||Current feedback||Power supply compensation||Voltage feedback shared with TRK||Direct PWM no feedback|
The input data is separated in the upper 8 bits and the lower 4 bits. Upper 8 bits (MSB sign 1 bit) will be put into 8-bit current DAC in every 5 MHz. The lower 4 bits will be put into one bit current DAC in sequence from upper to lower bit. This one bit DAC output with PWM in 1.25 MHz. At any PWM duty, 100%, 75%, 50%, 25%, or 0%, will be summed in 8-bit current DAC in every 1.25 MHz. Thus it takes 3.2 µs for all lower 4 bits summing to PWM output. As a result, 12-bit data is sampled in every PWM cycle. Example of sampling rate for FCS/TRK/TLT is Figure 55.
The output voltage (current) is commanded via programming to the DAC. All of the DAC input format is 12bit in two’s complement though some DAC has a low resolution. When 12 bits data is input 8 bits DAC, TPIC2010 recognizes four subordinate position bits (LSB) as 0. To arrange for 12bit DAC format, DSP should shift 8bit or 10 bit data to an appropriate bit position. The full scale is +/-1.0 V and driver gain is set 6. The output voltage (Vout) is given by the following equation:
|MSB DIGITAL INPUT (BIN) LSB||HEX||DEC||VDAC||ANALOG OUTPUT|
TPIC2010 is designed for that meets the requirements updating control data in 400 kHz. The example of control system parameter is Table 38. It takes 0.51 µs for transmit a 16-bit data packet to TPIC2010 with 35-MHz SCLK. Therefore, DSP can be sent four packets a 400-kHz interval. If SCLK is lower than 28.8 MHz, the system designer must reduce the packet quantity under three. For example, Focus/Truck command is updating in every 2.5 µs (400 kHz), and it is able to send another two kind of packet in this same slot. Figure 57 shows the example of the control timing when TPIC2010 is used.
|SIGNAL||BIT||UPDATE CYCLE (kHz)|
When VSPM is set a positive DAC code then it’ll be into acceleration mode. “IS” mode operates then the start-up circuit offers the special start-up pattern sequence to the driver in start-up, and then switch to spin-up mode by detecting the rotor position by BEMF signal from the spindle motor coil.
The spin-down and brake function also be controlled by DAC value VSPM. When it’s set the brake command to VSPM, driver goes into active-brake mode, then switch to short-brake mode in slow revolution speed, and then stop automatically. The FG signal is composed from EXOR of three-phase signal, and is output from XFG pin shown below.
The output PWM duty of Spindle is controlled by DAC code (VSPM). The gain in acceleration setting is always six times. However, the maximum output is restricted to P5V voltage. A dead band which output = 0 exists in the width of plus or minus 0x52 focusing on zero.
TPIC2010 provides auto short brake function which is selecting brake mode automatically by motor speed. Auto Short Brake is the intelligent brake function that includes two modes: short brake and active brake. When VSPM value is controlled more than equivalent 75% duty brake, deceleration is done by short brake under the rotation speed is over 3000 rpm. After deceleration, driver goes into Active-brake mode automatically by internal logic circuit under rotation speed is lower 2000 rpm. This function enables low power consumption and silent during braking.
|VSPM[11:0]||ROTATION SPEED (RPM)|
|≈ 0 TO 2000||≈ 3000|
|0x000 - 0xFAE||2-phase short brake||2-phase short brake|
|0xFAE - 0xA00||Active brake||Active brake|
|0xA00 - 0x800||Active brake||3-phase short brake|
LS mode is the low rotation mode which made the maximum 25% duty. When using SPM_LSMODE = 1, brake mode is always short brake. Figure 61 shows the output duty of LS mode.
The current limit circuit monitors the RCS voltage at ICOM pin, and limits the output current by reducing PWM duty, when detecting overcurrent conditions.
The Sled driver outputs the PWM pulse set as DAC code (VSLDx) with current feed back. The maximum output is restricted to 440 mA at 0x7FF and 0x800. A dead band which output = 0 exists in the width of plus or minus 0x33 focusing on zero.
This device has the function of end position detection for Sled and Collimator lens. This function aim to eliminate the position switch at PUH inner and collimator lens end position. This function is enabled by ENDDET_ENA = 1 with setting object actuator (ENDDET_SLCT = 0: for Sled ENDDET_SLCT = 1: for Step). When this function is enabled, internal logic will detect the sled out zero-cross point and at that time, internal BEMF detect circuit measures the BEMF level of stepping motor. There’re four threshold levels. If BEMF is lower than selected threshold, device recognizes motor at stop and ENDDET bit to 1. ENDDET bit will be cleared at the BEMF voltage exceed threshold again.
Load driver outputs the voltage with voltage feed back corresponding to the input DAC value. This channel has power voltage compensation thus it is suit for Slot-in type load control. This channel becomes active exclusively to other actuator channels. Load driver is shared with the TRK driver.
TPIC2010 support differential Tilt mode which output the value calculated from Focus and Tilt. Focus and Tilt can be set in differential mode by DIFF_TLT (REG74) = 1. Because Focus and Tilt are updated at the same time, the update interval of Tilt can be thinned out. Output data changes at after writing VFCS data. Therefore it’s necessary to write VFCS data when set VTLT. In differential mode, the output value is calculated as follows.
TPIC2010 has two channels synchronous step-down DC-DC converters. Two converters operate with a 120-degree turn-on phase shift of the PMOS (high side) transistors. It prevents the high side switches of both regulators to be turned on simultaneously, and therefore smooth the input current. This feature reduces the surge current drawn from the supply.
Switching frequency is 2.5 MHz. Because the ripple current in the coil can reduce, the smaller inductor value can be selected. And the inductor with lowest DC resistance can be selected for highest efficiency. And the regulators have fast transient response.
The V1Px is a DC-DC converter producing an output 1.0, 1.2, 1.5 V. It only requires an external inductor and bypass capacitor(s). The gate drivers and compensations are all internal to the chip. The required input supply is 5 V for P5V_SW. It has a soft start approximately about 0.8ms to limit the in-rush current when the regulator comes alive. The soft-start circuit uses the internal clock to profile its ramp.
It is able to up 2%, 3.8% and 5.5% of the output voltage by setting SWR1_VOUTUP (REG6D) for 1.2 V, 1.5 V. For 1.0 V, up to 1.3%, 2.4% and 3.3%.
V3P3 is a DC-DC converter producing an output of 3.3 V. It only requires an external inductor and bypass capacitor(s). The gate drivers and compensations are all internal to the chip. The required input supply is 5 V. It has a 0.8ms soft start to limit the in-rush current when the regulator comes alive. The soft-start circuit uses the internal clock to profile its ramp.
When not using DC-DC converter, it recommends that each terminal makes the following connection.
|PIN NAME||PIN NO.||CONNECTION|
The regulation mode called discontinuous regulation mode improves the conversion efficiency at a low current loading by changing regulation timing. Discontinuous mode is able to set 1 to SWx_MD_BURST (REG6D) bit. Figure 67 shows the discontinuous regulation action. The current consumption has been reduced by shortening the energizing time of driving FET. On the other hand, DC voltage ripple grows.
The device can output a specific signal to the GPOUT pin. To output a signal, choose a signal from REG6F by enabling first, then enable GPOUT_ENA. When two or more signals are set for GPOUT, the output is a logical sum
To begin the design process, determine the following:
After power up on 5-V supply, the following values may be written to the following registers to enable motors.
|A5V||AGND||Noise decoupling||1.0 (10%16V)||μF|
|P5V1||PGND||Noise decoupling||10.0 (10%16V)||μF|
|P5V2||PGND||Noise decoupling||10.0 (10%16V)||μF|
|P5V_SW||PGND_SW||Noise decoupling||10.0 (10%16V)||μF|
|P5V_SPM||PGND||Noise decoupling||10.0 (10%16V)||μF|
|SIOV||AGND||Noise decoupling||1.0 (10%16V)||μF|
|REG1PX||FB1PX||Inductor (ESR = 0.1 Ω) for DC-DC converter||1.5 (20% 1.2A)||µH|
|FB1PX||PGND_SW||Capacitor (ESR = 0.025 Ω)||10.0 (10%10V)||μF|
|CV3P3||AGND||Noise decoupling for internal 3.3V||0.1 (10%10V)||μF|
|ISENSE||PGND||Spindle current sense resistor||0.22 (1% 1W)||Ω|
|LOAD+||PGND||Prevent surge current||10000(10% 16V)||pF|
|LOAD-||PGND||Prevent surge current||10000(10% 16V)||pF|
|REG3P3||FB3P3||Inductor (ESR = 0.1 Ω)||1.5 (20% 1.2A)||µH|
|FB3P3||PGND_SW||Capacitor (ESR = 0.025 Ω)||10.0 (10% 10V)||μF|
|CP1||CP2||Charge pump capacitor||0.1 (10% 25V)||μF|
|CP3||P5V||Charge pump capacitor (P5V only, prohibit other power supply)||0.1 (10% 25V)||μF|
|COMPONENTS||RECOMMENDED VALUE||RECOMMENDED SUPPLIER||PART NUMBER|
|Inductor||1.5 (µH)||TAIYO YUDEN||BRL2518T1R5M|
|CSWO||Less than 4.7 µF||Since voltage will not rise within monitoring time if a big capacitance is connected on CSWO, the protected operation operates and repeat On / Off .|