SLIS170 December   2015 TPIC2010


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - Serial Port Voltage Levels
    6. 7.6  Electrical Characteristics - Common Part
    7. 7.7  Electrical Characteristics - Charge Pump
    8. 7.8  Electrical Characteristics - V1pXV DC-DC Converter
    9. 7.9  Electrical Characteristics - 3.3-V DC-DC Converter
    10. 7.10 Electrical Characteristics - Spindle Motor Driver Part
    11. 7.11 Electrical Characteristics - Sled Motor Driver Part
    12. 7.12 Electrical Characteristics - Focus/Tilt/Tracking/Driver Part
    13. 7.13 Electrical Characteristics - Load Driver Part
    14. 7.14 Electrical Characteristics - Stepping Motor Driver Part
    15. 7.15 Electrical Characteristics - Current Switch Part
    16. 7.16 Electrical Characteristics - LED Switch Part
    17. 7.17 Electrical Characteristics - Thermometer Part
    18. 7.18 Electrical Characteristics - Actuator Protection
    19. 7.19 Serial Port I/F Write Timing Requirements
    20. 7.20 Serial Port I/F Read Timing Requirements
    21. 7.21 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection Functions
        1. Undervoltage Lockout (UVLO)
        2. Overvoltage Protection (OVP)
        3. Overcurrent Protection (OCP)
        4. Thermal Protection (TSD)
        5. Actuator Temperature Protection (ACTTIMER)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset (POR)
        1. Power-Up Sequences
        2. XRESET
    5. 8.5 Programming
      1. 8.5.1 Function and Operation
        1. Serial Port Functional Description
        2. Write Operation
        3. Read Operation
        4. Write and Read Operation
    6. 8.6 Register Maps
      1. 8.6.1 Register State Transition
      2. 8.6.2 DAC Register (12-Bit Write Only)
      3. 8.6.3 Control Register (8-Bit Read/Write)
      4. 8.6.4 Detailed Description of Register
        1.  REG01 12-Bit DAC for Tilt
        2.  REG02 12-Bit DAC for Focus
        3.  REG03 12-Bit DAC for Tracking
        4.  REG04 12-Bit DAC for Sled1
        5.  REG05 12-Bit DAC for Sled2
        6.  REG06 12-Bit DAC for Stepping1
        7.  REG07 12-Bit DAC for Stepping2
        8.  REG08 12-Bit DAC for Spindle
        9.  REG09 12-Bit DAC for Load
        10. REG63 8-Bit Control Register for SpinAdj
        11. REG6C 8-Bit Control Register for EDetCfg
        12. REG6D 8-Bit Control Register for DCCfg
        13. REG6E 8-Bit Control Register for UtilCfg
        14. REG6F 8-Bit Control Register for MonitorSet
        15. REG70 8bit Control Register for DriverEna
        16. REG71 8-Bit Control Register for FuncEna
        17. REG72 8-Bit Control Register for ACTCfg
        18. REG73 8-Bit Control Register for Parm0
        19. REG74 8-Bit Control Register for SIFCfg
        20. REG76 8-Bit Control Register for WriteEna
        21. REG77 8-Bit Control Register for ClrReg
        22. REG78 8-Bit Control Register for ActTemp
        23. REG79 8-Bit Control Register for UVLOMon
        24. REG7A 8-Bit Control Register for ThPMon
        25. REG7B 8-Bit Control Register for OCPMon
        26. REG7C 8-Bit Control Register for TempMon
        27. REG7E 8-Bit Control Register for Version (REG7E)
        28. REG7F 8-Bit Control Register for Status (REG7F)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  DAC Type
      2. 9.1.2  Example Sampling Rate of 12-Bit DAC for FCS/TRK/TLT
      3. 9.1.3  Digital Input Coding
      4. 9.1.4  Example Timing of Target Control System
      5. 9.1.5  Spindle Motor Driver Part
        1. Spindle PWM Control
        2. Auto Short Brake Function
        3. Spindle Low Speed Mode
        4. Spindle Driver Current Limiting Circuit
      6. 9.1.6  Sled Driver Part
        1. End Detect Function
      7. 9.1.7  Load Driver Part
      8. 9.1.8  Focus/Track/Tilt Driver Part
        1. Input vs Output Duty
        2. Differential Tilt Mode
      9. 9.1.9  2-Channel Synchronous DC-DC Converter
        1. V1Px DC-DC Converter
        2. V3P3 DC-DC Converter
        3. Setup When Not Using DC-DC Converter
        4. Discontinuous Regulation Mode
      10. 9.1.10 Monitor Signal on GPOUT
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.


  • Operate every driver channel after 5 V power supplied and stable.
  • To calculate spindle motor driver over current limit (ILimit), use the following equation.
    ILimit = Internal REF voltage / RCS = 196 mV / 0.22 Ω ≈ 890 mA
  • Appropriate capacity of decoupling capacitor is required enough value of over 10 μF due to reduce influence of PWM switching noise. And the A5V pin needs to connect a filter of 1 μF. It is effective to put bypass capacitor (about 0.1 µF) near power pin (P5V_1, P5V_2, P5V_SW, P5V_SPM1, P5V_SPM2) for PWM switching noise reduction on power and GND line.
  • Much current flow to driver circuits, to consider as below matters.
    • Pattern-layout and line-impedance. And noise influence from supply line.

9.1 Application Information

9.1.1 DAC Type

TPIC2010 has nine channels of Actuator. Each channel is assigned to the most suitable DAC engine with a different type respectively. ACT(F/T/Ti) has 12-bit DAC. Upper 8 (MSB sign bit) are converted at a time in 5MHz and LSB 4 bits are output in sequence with 1.25-MHz PWM. SPIN, SLED and Load DAC has same DAC types and sampling rate with 312kHz. All channel (except SLED and STP) have x6 gain. The DAC for STP is 8-bits resolution output with 40 kHz PWM, no Feed Back. The Gain for STP is 5x relative to P5V voltage. Table 36 shows configuration of each actuator.

Table 36. List 5 DAC Type

Resolution 12bit 10bit 12bit 12bit 8bit
Type 8-bit over sampling 8-bit over sampling 8-bit over sampling 8-bit over sampling 1 bit Direct Duty PWM
Sampling 1.25M / 10bit
312K / 12bit
1.25M / 10bit
312K / 12bit
312K 312K 40 kHz
PWM freq 312 kHz 78 kHz 156 kHz 312 kHz 40 kHz
Out range ±6 V ±440 mA ±6 V ±6 V ±(P5V*1)
Feed back Voltage feedback Current feedback Power supply compensation Voltage feedback shared with TRK Direct PWM no feedback

9.1.2 Example Sampling Rate of 12-Bit DAC for FCS/TRK/TLT

The input data is separated in the upper 8 bits and the lower 4 bits. Upper 8 bits (MSB sign 1 bit) will be put into 8-bit current DAC in every 5 MHz. The lower 4 bits will be put into one bit current DAC in sequence from upper to lower bit. This one bit DAC output with PWM in 1.25 MHz. At any PWM duty, 100%, 75%, 50%, 25%, or 0%, will be summed in 8-bit current DAC in every 1.25 MHz. Thus it takes 3.2 µs for all lower 4 bits summing to PWM output. As a result, 12-bit data is sampled in every PWM cycle. Example of sampling rate for FCS/TRK/TLT is Figure 55.

TPIC2010 ex_12b_DAC_conv_slis170.gif Figure 55. Example of 12-Bit DAC Conversion Time (FCS/TRK/TLT)

9.1.3 Digital Input Coding

The output voltage (current) is commanded via programming to the DAC. All of the DAC input format is 12bit in two’s complement though some DAC has a low resolution. When 12 bits data is input 8 bits DAC, TPIC2010 recognizes four subordinate position bits (LSB) as 0. To arrange for 12bit DAC format, DSP should shift 8bit or 10 bit data to an appropriate bit position. The full scale is +/-1.0 V and driver gain is set 6. The output voltage (Vout) is given by the following equation:

Equation 1. TPIC2010 eq_01_lis170.gif
Equation 2. TPIC2010 eq_02_lis170.gif


  • bit[11:0] is the digital input value, range 000000000000b to 111111111111b.

Table 37. DAC Format

1000_0000_0000 0x800 –2048 –0.9995 –5.997
1000_0000_0001 0x801 –2047 –0.9995 –5.997
1111_1111_1111 0xFFF –1 –0.0005 –0.003
0000_0000_0000 0x000 0 0 0.000
0000_0000_0001 0x001 +1 +0.0005 +0.003
0111_1111_1110 0x7FE +2046 +0.9990 +5.994
0111_1111_1111 0x7FF +2047 +0.9995 +5.997
TPIC2010 out_V_vs_DAC_code_slis170.gif Figure 56. Output Voltage vs DAC Code

9.1.4 Example Timing of Target Control System

TPIC2010 is designed for that meets the requirements updating control data in 400 kHz. The example of control system parameter is Table 38. It takes 0.51 µs for transmit a 16-bit data packet to TPIC2010 with 35-MHz SCLK. Therefore, DSP can be sent four packets a 400-kHz interval. If SCLK is lower than 28.8 MHz, the system designer must reduce the packet quantity under three. For example, Focus/Truck command is updating in every 2.5 µs (400 kHz), and it is able to send another two kind of packet in this same slot. Figure 57 shows the example of the control timing when TPIC2010 is used.

Table 38. Example Timing of Target Control System

Focus 12 400
Track 12 400
Tilt 12 100
Sled1 10 100
Sled2 10 100
Spindle 12 100
Load 12
Step1 8 40
Step2 8 40
TPIC2010 ex_DAC_control_slis170.gif Figure 57. Example DAC Control

9.1.5 Spindle Motor Driver Part

When VSPM is set a positive DAC code then it’ll be into acceleration mode. “IS” mode operates then the start-up circuit offers the special start-up pattern sequence to the driver in start-up, and then switch to spin-up mode by detecting the rotor position by BEMF signal from the spindle motor coil.

The spin-down and brake function also be controlled by DAC value VSPM. When it’s set the brake command to VSPM, driver goes into active-brake mode, then switch to short-brake mode in slow revolution speed, and then stop automatically. The FG signal is composed from EXOR of three-phase signal, and is output from XFG pin shown below.

TPIC2010 spindle_op_seq_lis170.png Figure 58. Spindle Operating Sequence
  • It is recommended to use down-edge of FG signal for monitoring FG frequency. The FG terminal needs to be pull up to the appropriate supply voltage by external resistor.
  • Short Brake mode is asserted after 300ms of FG signal stays L-level in deceleration.
  • The FG Output is set to H-level in Sleep Mode in order to reduce sleep mode current.
  • This value is the nominal number of using motor with 16-poles.
  • First of all, power supply voltage of A5V/P5V must be supplied before any signals input.
  • Internal circuit starts after 800 µs(TYP) since XMUTE changed to “H”. Recommended marginal delay value is 1ms for being ready. Spindle PWM Control

The output PWM duty of Spindle is controlled by DAC code (VSPM). The gain in acceleration setting is always six times. However, the maximum output is restricted to P5V voltage. A dead band which output = 0 exists in the width of plus or minus 0x52 focusing on zero.

TPIC2010 spindle_PWM_ctrl_lis170.gif Figure 59. Spindle PWM Control Auto Short Brake Function

TPIC2010 provides auto short brake function which is selecting brake mode automatically by motor speed. Auto Short Brake is the intelligent brake function that includes two modes: short brake and active brake. When VSPM value is controlled more than equivalent 75% duty brake, deceleration is done by short brake under the rotation speed is over 3000 rpm. After deceleration, driver goes into Active-brake mode automatically by internal logic circuit under rotation speed is lower 2000 rpm. This function enables low power consumption and silent during braking.

Table 39. Brake Mode

≈ 0 TO 2000 ≈ 3000
0x000 - 0xFAE 2-phase short brake 2-phase short brake
0xFAE - 0xA00 Active brake Active brake
0xA00 - 0x800 Active brake 3-phase short brake
TPIC2010 brake_mode_sel_lis170.gif
This value is the nominal number of using motor with 16-poles motor.
Figure 60. Brake Mode Selections Spindle Low Speed Mode

LS mode is the low rotation mode which made the maximum 25% duty. When using SPM_LSMODE = 1, brake mode is always short brake. Figure 61 shows the output duty of LS mode.

TPIC2010 spindle_PWM_low_lis170.gif Figure 61. Spindle PWM Control (Low Speed Mode) Spindle Driver Current Limiting Circuit

The current limit circuit monitors the RCS voltage at ICOM pin, and limits the output current by reducing PWM duty, when detecting overcurrent conditions.

9.1.6 Sled Driver Part

The Sled driver outputs the PWM pulse set as DAC code (VSLDx) with current feed back. The maximum output is restricted to 440 mA at 0x7FF and 0x800. A dead band which output = 0 exists in the width of plus or minus 0x33 focusing on zero.

TPIC2010 sled_out_current_lis170.png Figure 62. Sled Output Current
  • Both outputs of SLED1/2 are “H” when input code is in dead band. End Detect Function

This device has the function of end position detection for Sled and Collimator lens. This function aim to eliminate the position switch at PUH inner and collimator lens end position. This function is enabled by ENDDET_ENA = 1 with setting object actuator (ENDDET_SLCT = 0: for Sled ENDDET_SLCT = 1: for Step). When this function is enabled, internal logic will detect the sled out zero-cross point and at that time, internal BEMF detect circuit measures the BEMF level of stepping motor. There’re four threshold levels. If BEMF is lower than selected threshold, device recognizes motor at stop and ENDDET bit to 1. ENDDET bit will be cleared at the BEMF voltage exceed threshold again.

TPIC2010 tim_sled_end_det_lis170.gif Figure 63. Timing of Sled End Detection
  • For the purpose of getting correct stepping motor BEMF, we recommend to choose more than 110Hz (440pps) control frequency. However this control frequency depends on the stepping motor characteristic.
  • BEMF detection level is selectable 22, 46, 86 mV.
TPIC2010 tim_step_end_det_lis170.png Figure 64. Timing of Step End Detection
  • Recommended control speed is around 1200 pps for getting correct BEMF level. It depends on the stepping motor characteristic. Please evaluate on your condition adequately.
  • BEMF detection level is selectable 19, 39, 60 mV.

9.1.7 Load Driver Part

Load driver outputs the voltage with voltage feed back corresponding to the input DAC value. This channel has power voltage compensation thus it is suit for Slot-in type load control. This channel becomes active exclusively to other actuator channels. Load driver is shared with the TRK driver.

TPIC2010 load_out_duty_lis170.png Figure 65. Load Output Duty
  • Output voltage is controlled by PWM
  • Both LOAD+ and LOAD- are connected to PGND through the internal clamp diode respectively.

9.1.8 Focus/Track/Tilt Driver Part Input vs Output Duty

TPIC2010 slis166_fcs_trk_tlt_output_duty.gif Figure 66. FCS/TRK/TLT Output Duty Differential Tilt Mode

TPIC2010 support differential Tilt mode which output the value calculated from Focus and Tilt. Focus and Tilt can be set in differential mode by DIFF_TLT (REG74) = 1. Because Focus and Tilt are updated at the same time, the update interval of Tilt can be thinned out. Output data changes at after writing VFCS data. Therefore it’s necessary to write VFCS data when set VTLT. In differential mode, the output value is calculated as follows.

Equation 3. FCS_OUT = (VFCS + VTLT) × 6
Equation 4. TLT_OUT = (VFCS – VTLT) × 6

9.1.9 2-Channel Synchronous DC-DC Converter

TPIC2010 has two channels synchronous step-down DC-DC converters. Two converters operate with a 120-degree turn-on phase shift of the PMOS (high side) transistors. It prevents the high side switches of both regulators to be turned on simultaneously, and therefore smooth the input current. This feature reduces the surge current drawn from the supply.

Switching frequency is 2.5 MHz. Because the ripple current in the coil can reduce, the smaller inductor value can be selected. And the inductor with lowest DC resistance can be selected for highest efficiency. And the regulators have fast transient response. V1Px DC-DC Converter

The V1Px is a DC-DC converter producing an output 1.0, 1.2, 1.5 V. It only requires an external inductor and bypass capacitor(s). The gate drivers and compensations are all internal to the chip. The required input supply is 5 V for P5V_SW. It has a soft start approximately about 0.8ms to limit the in-rush current when the regulator comes alive. The soft-start circuit uses the internal clock to profile its ramp.

It is able to up 2%, 3.8% and 5.5% of the output voltage by setting SWR1_VOUTUP[2] (REG6D) for 1.2 V, 1.5 V. For 1.0 V, up to 1.3%, 2.4% and 3.3%. V3P3 DC-DC Converter

V3P3 is a DC-DC converter producing an output of 3.3 V. It only requires an external inductor and bypass capacitor(s). The gate drivers and compensations are all internal to the chip. The required input supply is 5 V. It has a 0.8ms soft start to limit the in-rush current when the regulator comes alive. The soft-start circuit uses the internal clock to profile its ramp. Setup When Not Using DC-DC Converter

When not using DC-DC converter, it recommends that each terminal makes the following connection.

Table 40. Not Using DC-DC Converter

SWR_SEQ1 18 5V (H)
SWR_SEQ2 19 5V (H)
V1PXSEL 20 5V (H)
P5V_SW 26 5V
FB3P3 30 OPEN Discontinuous Regulation Mode

The regulation mode called discontinuous regulation mode improves the conversion efficiency at a low current loading by changing regulation timing. Discontinuous mode is able to set 1 to SWx_MD_BURST (REG6D) bit. Figure 67 shows the discontinuous regulation action. The current consumption has been reduced by shortening the energizing time of driving FET. On the other hand, DC voltage ripple grows.

TPIC2010 disc_reg_mode_lis170.gif Figure 67. Discontinuous Regulation Mode

9.1.10 Monitor Signal on GPOUT

The device can output a specific signal to the GPOUT pin. To output a signal, choose a signal from REG6F by enabling first, then enable GPOUT_ENA. When two or more signals are set for GPOUT, the output is a logical sum

9.2 Typical Application

TPIC2010 typ_app_slis170.gif Figure 68. Typical Application Circuit

9.2.1 Design Requirements

To begin the design process, determine the following:

  1. Motor configuration: The user can use all motor channels or some of them.
  2. Power up devices with a 5-V supply.

9.2.2 Detailed Design Procedure

After power up on 5-V supply, the following values may be written to the following registers to enable motors.

  1. Set WRITE_ENABLE = 1 on REG76 via SPI.
  2. Set XSLEEP = 1 at REG70
  3. Enable motor channel by ENA_XXX bits on REG70
  4. Change the DAC settings for each motor in REG01-0B. Then, output channels will start driving load.

Table 41. Recommended External Components

A5V AGND Noise decoupling 1.0 (10%16V) μF
P5V1 PGND Noise decoupling 10.0 (10%16V) μF
P5V2 PGND Noise decoupling 10.0 (10%16V) μF
P5V_SW PGND_SW Noise decoupling 10.0 (10%16V) μF
P5V_SPM PGND Noise decoupling 10.0 (10%16V) μF
SIOV AGND Noise decoupling 1.0 (10%16V) μF
REG1PX FB1PX Inductor (ESR = 0.1 Ω) for DC-DC converter 1.5 (20% 1.2A) µH
FB1PX PGND_SW Capacitor (ESR = 0.025 Ω) 10.0 (10%10V) μF
CV3P3 AGND Noise decoupling for internal 3.3V 0.1 (10%10V) μF
ISENSE PGND Spindle current sense resistor 0.22 (1% 1W) Ω
LOAD+ PGND Prevent surge current 10000(10% 16V) pF
LOAD- PGND Prevent surge current 10000(10% 16V) pF
REG3P3 FB3P3 Inductor (ESR = 0.1 Ω) 1.5 (20% 1.2A) µH
FB3P3 PGND_SW Capacitor (ESR = 0.025 Ω) 10.0 (10% 10V) μF
CP1 CP2 Charge pump capacitor 0.1 (10% 25V) μF
CP3 P5V Charge pump capacitor (P5V only, prohibit other power supply) 0.1 (10% 25V) μF

Table 42. Specific for DC-DC Converter Components

Inductor 1.5 (µH) TAIYO YUDEN BRL2518T1R5M
Capacitor 10 (µF) MURATA GRM21BB31A106KE18L

Table 43. Restriction of Selection Parts

CSWO Less than 4.7 µF Since voltage will not rise within monitoring time if a big capacitance is connected on CSWO, the protected operation operates and repeat On / Off .

9.2.3 Application Curves

TPIC2010 D003_SLIS170.gif
Figure 69. DAC Code vs Duty Cycle for TLT Outputs
TPIC2010 D004_SLIS170.gif
Figure 70. DAC Code vs Duty Cycle for LOAD Outputs