SBVS124A November   2008  – May 2016 TPS2115A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Circuits
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 N-Channel MOSFETs
      2. 8.3.2 Cross-Conduction Blocking
      3. 8.3.3 Reverse-Conduction Blocking
      4. 8.3.4 Charge Pump
      5. 8.3.5 Current Limiting
      6. 8.3.6 Output Voltage Slew-Rate Control
    4. 8.4 Device Functional Modes
      1. 8.4.1 Auto-Switching Mode
      2. 8.4.2 Manual Switching Mode
  9. 9 Application and Information
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

  • For the first supply input (IN1), place the 0.1-μF bypass capacitor between the IN1 and GND as close as possible ensuring a low-impedance trace.
  • For the second supply input (IN2), place the 0.1-μF bypass capacitor between the IN2 and GND as close as possible ensuring a low-impedance trace.
  • Place a high-value capacitor and a 0.1-μF bypass capacitor between OUT and GND. The recommendation is to use the high-value capacitor when expecting large-load transients on the output. This trace should be low-impedance to the load.
  • Place the resistor used to set the current limit between ILIM and GND. Make sure the traces routing the RILIM resistor to the device are as short as possible to reduce parasitic effects on the current limit accuracy.

11.2 Layout Example

TPS2115A-Q1 layout_2115A.gif Figure 24. TPS2115A-Q1 Layout Example