The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and classification. The converter circuits discharge CIN, CVC, and CVB while the PD is unpowered. Thus VVDD-VRTN will be a small voltage just after full voltage is applied to the PD, as seen in Figure 22. The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When VVDD rises above the UVLO turnon threshold (VUVLO-R, about 35 V) with RTN high, the TPS23754 device enables the hotswap MOSFET with an approximately 140-mA (inrush) current limit as seen in Figure 24. Converter switching is disabled while CIN charges and VRTN falls from VVDD to nearly VVSS, however the converter start-up circuit is allowed to charge CVC (the bootstrap start-up capacitor). Additional loading applied between VVDD and VRTN during the inrush state may prevent successful PD and subsequent converter start-up. Converter switching is allowed if the PD is not in inrush, OTSD is not active, and the VC UVLO permits it. Once the inrush current falls about 10% less than the inrush current limit, the PD current limit switches to the operational level (about 970 mA). Continuing the start-up sequence shown in Figure 24, VVC continues to rise until the start-up threshold (VCUV, about 15 V or about 9 V) is exceeded, turning the start-up source off and enabling switching. The VB regulator is always active, powering the internal converter circuits as VVC rises. There is a slight delay between the removal of charge current and the start of switching as the soft-start ramp sweeps above the VZDC threshold. VVC falls as it powers both the internal circuits and the switching MOSFET gates. If the converter control bias output rises to support VVC before it falls to VCUV – VCUVH (about 8.5 V or about 5.5 V), a successful start-up occurs. T2P in Figure 22 (Figure 27, VT2P-OUT) becomes active within tT2P from the start of switching, indicating that a type 2 PSE or an adapter is plugged in.
If VVDD- VVSS drops below the lower PoE UVLO (VUVLO-R - VUVLO-H, about 30.5 V), the hotswap MOSFET is turned off, but the converter will still run. The converter will stop if VVC falls below the converter UVLO (VCUV – VCUVH, about 8.5 V or about 5.5 V), the hotswap is in inrush current limit, 0% duty cycle is demanded by VCTL (VCTL < VZDC, about 1.5 V), or the converter is in thermal shutdown.