SLUSC25A February   2015  – August 2017 TPS2388

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
    2. 5.1 Detailed Pin Description
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Timing Diagrams
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Port Remapping
      2. 8.3.2 Port Power Priority
      3. 8.3.3 A/D Converter
      4. 8.3.4 I2C Watchdog
      5. 8.3.5 Foldback Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Port Operating Modes
        1. 8.4.1.1 Semiauto
        2. 8.4.1.2 Manual
        3. 8.4.1.3 Power Off
      2. 8.4.2 Detection
      3. 8.4.3 Classification
      4. 8.4.4 DC Disconnect
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1  Complete Register Set
      2. 8.6.2  INTERRUPT Register
        1. Table 4. INTERRUPT Register Field Descriptions
      3. 8.6.3  INTERRUPT MASK Register
        1. Table 5. INTERRUPT MASK Register Field Descriptions
      4. 8.6.4  POWER EVENT Register
        1. Table 6. POWER EVENT Register Field Descriptions
      5. 8.6.5  DETECTION EVENT Register
        1. Table 7. DETECTION EVENT Register Field Descriptions
      6. 8.6.6  FAULT EVENT Register
        1. Table 8. FAULT EVENT Register Field Descriptions
      7. 8.6.7  START/ILIM EVENT Register
        1. Table 9. START/ILIM EVENT Register Field Descriptions
      8. 8.6.8  SUPPLY EVENT Register
        1. Table 10. SUPPLY EVENT Register Field Descriptions
      9. 8.6.9  PORT 1 STATUS Register
      10. 8.6.10 PORT 2 STATUS Register
      11. 8.6.11 PORT 3 STATUS Register
      12. 8.6.12 PORT 4 STATUS Register
        1. Table 11. PORT STATUS Register Field Descriptions
      13. 8.6.13 POWER STATUS Register
        1. Table 12. POWER STATUS Register Field Descriptions
      14. 8.6.14 Pin Status Register
        1. Table 13. Pin Status Register Field Descriptions
      15. 8.6.15 OPERATING MODE Register
        1. Table 14. OPERATING MODE Register Field Descriptions
      16. 8.6.16 DISCONNECT ENABLE Register
        1. Table 15. DISCONNECT ENABLE Register Field Descriptions
      17. 8.6.17 DETECT/CLASS ENABLE Register
        1. Table 16. DETECT/CLASS ENABLE Register Field Descriptions
      18. 8.6.18 Port Power Priority/ICUT Disable Register Name
        1. Table 17. Port Power Priority/ICUT Disable Register Field Descriptions
      19. 8.6.19 TIMING CONFIGURATION Register
        1. Table 18. TIMING CONFIGURATION Register Field Descriptions
      20. 8.6.20 GENERAL MASK Register
        1. Table 19. GENERAL MASK Register Field Descriptions
      21. 8.6.21 DETECT/CLASS RESTART Register
        1. Table 20. DETECT/CLASS RESTART Register Field Descriptions
      22. 8.6.22 POWER ENABLE Register
        1. Table 21. POWER ENABLE Register Field Descriptions
      23. 8.6.23 RESET Register
        1. Table 22. RESET Register Field Descriptions
      24. 8.6.24 ID Register
        1. Table 23. ID Register Field Descriptions
      25. 8.6.25 Police 21 Configuration Register
      26. 8.6.26 Police 43 Configuration Register
        1. Table 24. Police 43 Register Field Descriptions
      27. 8.6.27 IEEE Power Enable Register
        1. Table 25. IEEE Power Enable Register Field Descriptions
      28. 8.6.28 Power-on Fault Register
        1. Table 26. Power-on Fault Register Field Descriptions
      29. 8.6.29 PORT RE-MAPPING Register
        1. Table 27. PORT RE-MAPPING Register Field Descriptions
      30. 8.6.30 Port 21 Multi Bit Priority Register
      31. 8.6.31 Port 43 Multi Bit Priority Register
        1. Table 28. Port 43 Register Field Descriptions
      32. 8.6.32 TEMPERATURE Register
        1. Table 29. TEMPERATURE Register Field Descriptions
      33. 8.6.33 INPUT VOLTAGE Register
        1. Table 30. INPUT VOLTAGE Register Field Descriptions
      34. 8.6.34 PORT 1 CURRENT Register
      35. 8.6.35 PORT 2 CURRENT Register
      36. 8.6.36 PORT 3 CURRENT Register
      37. 8.6.37 PORT 4 CURRENT Register
        1. Table 31. PORT 4 CURRENT Register Field Descriptions
      38. 8.6.38 PORT 1 VOLTAGE Register
      39. 8.6.39 PORT 2 VOLTAGE Register
      40. 8.6.40 PORT 3 VOLTAGE Register
      41. 8.6.41 PORT 4 VOLTAGE Register
        1. Table 32. PORT 4 VOLTAGE Register Field Descriptions
      42. 8.6.42 PoE Plus Register
        1. Table 33. PoE Plus Register Field Descriptions
      43. 8.6.43 FIRMWARE REVISION
        1. Table 34. FIRMWARE REVISION Register Field Descriptions
      44. 8.6.44 I2C WATCHDOG Register
        1. Table 35. I2C WATCHDOG Register Field Descriptions
      45. 8.6.45 DEVICE ID Register
        1. Table 36. DEVICE ID Register Field Descriptions
      46. 8.6.46 PORT 1 DETECT RESISTANCE Register
      47. 8.6.47 PORT 2 DETECT RESISTANCE Register
      48. 8.6.48 PORT 3 DETECT RESISTANCE Register
      49. 8.6.49 PORT 4 DETECT RESISTANCE Register
        1. Table 37. PORT 4 DETECT RESISTANCE Register Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Introduction to PoE
      2. 9.1.2 TPS2388 Application
      3. 9.1.3 Kelvin Current Sensing Resistor
      4. 9.1.4 Connections on Unused Ports
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Pin Bypass Capacitors
        2. 9.2.2.2 Per Port Components
        3. 9.2.2.3 System Level Components (not shown in the schematic diagrams)
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VPWR
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Port Current Kelvin Sensing
    2. 11.2 Layout Example
      1. 11.2.1 Component Placement and Routing Guidelines
        1. 11.2.1.1 Power Pin Bypass Capacitors
        2. 11.2.1.2 Per-Port Components
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Pin Description

The following descriptions refer to the pinout and the functional block diagram.

DRAIN1-DRAIN8: Port 1-8 output voltage monitor and detect sense. Used to measure the port output voltage, for port voltage monitoring, port power good detection and foldback action. Detection probe currents also flow into this pin.

The TPS2388 uses an innovative 4-point technique to provide reliable PD detection. The discovery is performed by sinking two different current levels via the DRAINn pin, while the PD voltage is measured from VPWR to DRAINn. The 4-point measurement provides the capability to avoid powering a capacitive or legacy load. Also, while in semiauto mode, if prior to starting a new detection cycle the port voltage is >2.5 V, an internal 100-kΩ resistor is connected in parallel with the port and a 400-ms detect backoff period is applied to allow the port capacitor to be discharged before the detection cycle starts.

There is an internal resistor between each DRAINn pin and VPWR in any operating mode except during detection or while the port is ON. If the port n is not used, DRAINn can be left floating or tied to AGND.

GAT1-GAT8: Port 1-8 gate drive output is used for external N-channel MOSFET gate control. At port turn on, it is driven positive by a low current source to turn the MOSFET on. GATn is pulled low whenever any of the input supplies are low or if an overcurrent timeout has occurred. GATn is also pulled low if its port is turned off by use of manual shutdown inputs. Leave floating if unused.

For a robust design, a current foldback function limits the power dissipation of the MOSFET during low resistance load or a short-circuit event. During inrush, the foldback mechanism measures the port voltage across VPWR and DRAINn to reduce the current limit threshold as shown in Figure 17.

When ICUT threshold is exceeded while a port is on, a timer starts. During that time, linear current limiting ensures the current does not exceed ILIM combined with current foldback action. When the timer reaches its tOVLD (or tSTART if at port turn on) limit, the part shuts off. When the port current goes below ICUT, the counter counts down at a rate 1/16th of the increment rate and it must reach a count of 0 before the port can be turned on again.

The fast overload protection is for major faults like a direct short. This forces the MOSFET into current limit in less than a microsecond.

The circuit leakage paths between the GATn pin and any nearby DRAINn pin, GND or Kelvin point connection must be minimized (<250 nA), to ensure correct MOSFET control.

INT: This interrupt output pin asserts low when a bit in the interrupt register is asserted. This output is open-drain.

KSENSA, KSENSB, KSENSC, KSENSD: Kelvin point connection used to perform a differential voltage measurement across the associated current sense resistors.

Each KSENS is shared between two neighbor SEN pins as following: KSENSA with SEN1 and SEN2, KSENSB with SEN3 and SEN4, KSENSC with SEN5 and SEN6, KSENSD with SEN7 and SEN8. To optimize the accuracy of the measurement, take care with the PCB layout to minimize the impact of the PCB traces' resistance.

OSS: Fast shutdown, active high. This pin is internally pulled down to DGND, with an internal 1-µs to 5-µs deglitch filter.

The Port Power Priority/ICUT Disable register is used to determine which port is shut down in response to an external assertion of the OSS fast shutdown signal. The turn off procedure is similar to a port reset using Reset command (1Ah register).

RESET: Reset input, active low. When asserted, the TPS2388 resets, turning off all ports and forcing the registers to their power-up state. This pin is internally pulled up to VDD, with internal 1-µs to 5-µs deglitch filter. The designer can use an external RC network to delay the turn-on. There is also an internal power-on-reset which is independent of the RESET input.

NOTE

During the first 5 ms after RESET has been asserted, if a port is turned on using the Power Enable command (0x19), TI recommends to wait for the expiration of that 5-ms initial period before sending any subsequent Detect/Class Restart or Detect/Class Enable command.

SCL: Serial clock input for I2C bus.

SDAI: Serial data input for I2C bus. This pin can be connected to SDAO for non-isolated systems.

SDAO: Open-drain I2C bus output data line. Requires an external resistive pull-up. The TPS2388 uses separate SDAO and SDAI lines to allow optoisolated I2C interface. SDAO can be connected to SDAI for non-isolated systems.

A4-A1: I2C bus address inputs. These pins are internally pulled up to VDD. See Pin Status Register for more details.

SEN1-8: Port current sense input relative to KSENSn (see KSENSn description). A differential measurement is performed using KSENSA-D Kelvin point connection. Monitors the external MOSFET current by use of a 0.255-Ω current sense resistor connected to DGND. Used by current foldback engine and also during classification. Can be used to perform load current monitoring via A/D conversion.

Note that a classification is done while using the external MOSFET so that doing a classification on more than one port at same time is possible without overdissipation in the TPS2388. For the current limit with foldback function, there is an internal 2-µS analog filter on the SEN1-8 pins to provide glitch filtering. For measurements through an A/D converter, an anti-aliasing filter is present on the SEN1-8 pins. This includes the port-powered current monitoring, port policing, and DC disconnect.

If the port is not used, tie SENn to AGND.

VDD: 3.3-V logic power supply input.

VPWR: High voltage power supply input. Nominally 48 V.