SLVSF02D
March 2019 – May 2020
TPS23881
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Simplified Schematic
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
6.1
Detailed Pin Description
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics
8
Parameter Measurement Information
8.1
Timing Diagrams
9
Detailed Description
9.1
Overview
9.1.1
Operating Modes
9.1.1.1
Auto
9.1.1.2
Semiauto
9.1.1.3
Manual/Diagnostic
9.1.1.4
Power Off
9.1.2
PoE Compliance Terminology
9.1.3
Channel versus Port Terminology
9.1.4
Requested Class versus Assigned Class
9.1.5
Power Allocation and Power Demotion
9.1.6
Programmable SRAM
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Port Remapping
9.3.2
Port Power Priority
9.3.3
Analog-to-Digital Converters (ADC)
9.3.4
I2C Watchdog
9.3.5
Current Foldback Protection
9.4
Device Functional Modes
9.4.1
Detection
9.4.2
Connection Check
9.4.3
Classification
9.4.4
DC Disconnect
9.5
I2C Programming
9.5.1
I2C Serial Interface
9.6
Register Maps
9.6.1
Complete Register Set
9.6.2
Detailed Register Descriptions
9.6.2.1
INTERRUPT Register
Table 6.
INTERRUPT Register Field Descriptions
9.6.2.2
INTERRUPT MASK Register
Table 7.
INTERRUPT MASK Register Field Descriptions
9.6.2.3
POWER EVENT Register
Table 8.
POWER EVENT Register Field Descriptions
9.6.2.4
DETECTION EVENT Register
Table 9.
DETECTION EVENT Register Field Descriptions
9.6.2.5
FAULT EVENT Register
Table 10.
FAULT EVENT Register Field Descriptions
9.6.2.6
START/ILIM EVENT Register
Table 11.
START/ILIM EVENT Register Field Descriptions
9.6.2.7
SUPPLY and FAULT EVENT Register
Table 12.
SUPPLY and FAULT EVENT Register Field Descriptions
9.6.2.7.1
Detected SRAM Faults and "Safe Mode"
9.6.2.7.1.1
ULA (Ultra Low Alpha) Package Option: TPS23881A
9.6.2.8
CHANNEL 1 DISCOVERY Register
9.6.2.9
CHANNEL 2 DISCOVERY Register
9.6.2.10
CHANNEL 3 DISCOVERY Register
9.6.2.11
CHANNEL 4 DISCOVERY Register
Table 13.
CHANNEL n DISCOVERY Register Field Descriptions
9.6.2.12
POWER STATUS Register
Table 14.
POWER STATUS Register Field Descriptions
9.6.2.13
PIN STATUS Register
Table 15.
PIN STATUS Register Field Descriptions
9.6.2.14
OPERATING MODE Register
Table 16.
OPERATING MODE Register Field Descriptions
9.6.2.15
DISCONNECT ENABLE Register
Table 20.
DISCONNECT ENABLE Register Field Descriptions
9.6.2.16
DETECT/CLASS ENABLE Register
Table 21.
DETECT/CLASS ENABLE Register Field Descriptions
9.6.2.17
Power Priority / 2Pair PCUT Disable Register Name
Table 22.
Power Priority / 2P-PCUT Disable Register Field Descriptions
9.6.2.18
TIMING CONFIGURATION Register
Table 24.
TIMING CONFIGURATION Register Field Descriptions
9.6.2.19
GENERAL MASK Register
Table 25.
GENERAL MASK Register Field Descriptions
9.6.2.20
DETECT/CLASS RESTART Register
Table 27.
DETECT/CLASS RESTART Register Field Descriptions
9.6.2.21
POWER ENABLE Register
Table 28.
POWER ENABLE Register Field Descriptions
9.6.2.22
RESET Register
Table 32.
RESET Register Field Descriptions
9.6.2.23
ID Register
Table 34.
ID Register Field Descriptions
9.6.2.24
Connection Check and Auto Class Status Register
Table 35.
Connection Check and Auto Class Field Descriptions
9.6.2.25
2-Pair Police Ch-1 Configuration Register
9.6.2.26
2-Pair Police Ch-2 Configuration Register
9.6.2.27
2-Pair Police Ch-3 Configuration Register
9.6.2.28
2-Pair Police Ch-4 Configuration Register
Table 36.
2-Pair Policing Register Fields Descriptions
9.6.2.29
Capacitance (Legacy PD) Detection
Table 39.
Capacitance Detection Register Field Descriptions
9.6.2.30
Power-on Fault Register
Table 40.
Power-on Fault Register Field Descriptions
9.6.2.31
PORT RE-MAPPING Register
Table 41.
PORT RE-MAPPING Register Field Descriptions
9.6.2.32
Channels 1 and 2 Multi Bit Priority Register
9.6.2.33
Channels 3 and 4 Multi Bit Priority Register
Table 42.
Channels n MBP Register Field Descriptions
9.6.2.34
4-Pair Wired and Port Power Allocation Register
Table 44.
4-Pair Wired and Power Allocation Register Field Descriptions
9.6.2.35
4-Pair Police Ch-1 and 2 Configuration Register
9.6.2.36
4-Pair Police Ch-3 and 4 Configuration Register
Table 46.
4-Pair Police Register Field Descriptions
9.6.2.37
TEMPERATURE Register
Table 48.
TEMPERATURE Register Field Descriptions
9.6.2.38
4-Pair Fault Configuration Register
Table 49.
4-Pair Fault Register Field Descriptions
9.6.2.39
INPUT VOLTAGE Register
Table 50.
INPUT VOLTAGE Register Field Descriptions
9.6.2.40
CHANNEL 1 CURRENT Register
9.6.2.41
CHANNEL 2 CURRENT Register
9.6.2.42
CHANNEL 3 CURRENT Register
9.6.2.43
CHANNEL 4 CURRENT Register
Table 51.
CHANNEL n CURRENT Register Field Descriptions
9.6.2.44
CHANNEL 1 VOLTAGE Register
9.6.2.45
CHANNEL 2 VOLTAGE Register
9.6.2.46
CHANNEL 3 VOLTAGE Register
9.6.2.47
CHANNEL 4 VOLTAGE Register
Table 52.
CHANNEL n VOLTAGE Register Field Descriptions
9.6.2.48
2x FOLDBACK SELECTION Register
Table 53.
2x FOLDBACK SELECTION Register Field Descriptions
9.6.2.49
FIRMWARE REVISION Register
Table 54.
FIRMWARE REVISION Register Field Descriptions
9.6.2.50
I2C WATCHDOG Register
Table 55.
I2C WATCHDOG Register Field Descriptions
9.6.2.51
DEVICE ID Register
Table 57.
DEVICE ID Register Field Descriptions
9.6.2.52
CHANNEL 1 DETECT RESISTANCE Register
9.6.2.53
CHANNEL 2 DETECT RESISTANCE Register
9.6.2.54
CHANNEL 3 DETECT RESISTANCE Register
9.6.2.55
CHANNEL 4 DETECT RESISTANCE Register
Table 58.
DETECT RESISTANCE Register Fields Descriptions
9.6.2.56
CHANNEL 1 DETECT CAPACITANCE Register
9.6.2.57
CHANNEL 2 DETECT CAPACITANCE Register
9.6.2.58
CHANNEL 3 DETECT CAPACITANCE Register
9.6.2.59
CHANNEL 4 DETECT CAPACITANCE Register
Table 59.
DETECT CAPACITANCE Register Fields Descriptions
9.6.2.60
CHANNEL 1 ASSIGNED CLASS Register
9.6.2.61
CHANNEL 2 ASSIGNED CLASS Register
9.6.2.62
CHANNEL 3 ASSIGNED CLASS Register
9.6.2.63
CHANNEL 4 ASSIGNED CLASS Register
Table 60.
CHANNEL n ASSIGNED CLASS Register Field Descriptions
9.6.2.64
AUTO CLASS CONTROL Register
Table 63.
AUTO CLASS CONTROL Register Field Descriptions
9.6.2.65
CHANNEL 1 AUTO CLASS POWER Register
9.6.2.66
CHANNEL 2 AUTO CLASS POWER Register
9.6.2.67
CHANNEL 3 AUTO CLASS POWER Register
9.6.2.68
CHANNEL 4 AUTO CLASS POWER Register
Table 65.
AUTO CLASS POWER Register Fields Descriptions
9.6.2.69
ALTERNATIVE FOLDBACK Register
Table 66.
ALTERNATIVE FOLDBACK Register Field Descriptions
9.6.2.70
SRAM CONTROL Register
Table 67.
SRAM CONTROL Register Field Descriptions
9.6.2.70.1
SRAM START ADDRESS (LSB) Register
9.6.2.70.2
SRAM START ADDRESS (MSB) Register
Table 68.
SRAM START ADDRESS Register Field Descriptions
10
Application and Implementation
10.1
Application Information
10.1.1
Introduction to PoE
10.1.1.1
2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Connections on Unused Channels
10.2.2.2
Power Pin Bypass Capacitors
10.2.2.3
Per Port Components
10.2.2.4
System Level Components (not shown in the schematic diagrams)
10.2.3
Application Curves
11
Power Supply Recommendations
11.1
VDD
11.2
VPWR
12
Layout
12.1
Layout Guidelines
12.1.1
Kelvin Current Sensing Resistors
12.2
Layout Example
12.2.1
Component Placement and Routing Guidelines
12.2.1.1
Power Pin Bypass Capacitors
12.2.1.2
Per-Port Components
13
Device and Documentation Support
13.1
Documentation Support
13.1.1
Related Documentation
13.2
Receiving Notification of Documentation Updates
13.3
Support Resources
13.4
Trademarks
13.5
Electrostatic Discharge Caution
13.6
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RTQ|56
MPQF168D
Thermal pad, mechanical data (Package|Pins)
RTQ|56
QFND490A
Orderable Information
slvsf02d_oa
slvsf02d_pm
1
Features
IEEE 802.3bt PSE solution for PoE 2
Type 3 or Type 4
Power Over Ethernet applications
Eight independent PSE channels
Compatible with TI's
FirmPSE
system firmware
SRAM Programmable memory
Programmable power limiting accuracy
±2.5%
200-mΩ Current sense resistor
Legacy PD capacitance measurement
Selectable 2-pair or 4-pair port power allocations
15.4 W, 30 W, 45 W, 60 W, 75 W or 90 W
Single and dual signature PD compatibility
Dedicated 14-bit integrating current ADC per port
Noise immune MPS for DC disconnect
2% Current sensing accuracy
1- or 3-Bit fast port shutdown input
Auto-class discovery and power measurement
Inrush and operational foldback protection
Flexible processor controlled operating modes
Auto, semi auto and manual / diagnostic
Per Port voltage monitoring and telemetry
–40°C to +125°C Temperature operation
Ultra Low Alpha (ULA)
packaging (TPS23881A)