SLVSCU3 December   2014 TPS2592ZA

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Application Schematic
  5. 5 Revision History
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 GND
      2. 9.3.2 VIN
      3. 9.3.3 dV/dT
      4. 9.3.4 BFET
      5. 9.3.5 EN/UVLO
      6. 9.3.6 ILIM
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Simple 2.1-A eFuse Protection for Set Top Boxes
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Step by Step Design Procedure
          2. 10.2.1.2.2 Programming the Current-Limit Threshold: RILIM Selection
          3. 10.2.1.2.3 Undervoltage Lockout Set Point
          4. 10.2.1.2.4 Setting Output Voltage Ramp Time (TdVdT)
            1. 10.2.1.2.4.1 Case 1: Start-up without Load: Only Output Capacitance COUT Draws Current During Start-up
            2. 10.2.1.2.4.2 Case 2: Start-up with Load: Output Capacitance COUT and Load Draws Current During Start-up
        3. 10.2.1.3 Support Component Selection - CVIN
        4. 10.2.1.4 Application Curves
    3. 10.3 Maximum Device Power Dissipation Considerations
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
    2. 11.2 Output Short-Circuit Measurements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The TPA2592xx is a smart eFuse. It is typically used for Hot-Swap and Power rail protection applications. It operates from 4.5 V to 18 V with programmable current limit and undervoltage protection. The device aids in controlling the in-rush current and provides precise current limiting during overload conditions for systems such as Set-Top-Box, DTVs, Gaming Consoles, SSDs/HDDs and Smart Meters. The device also provides robust protection for multiple faults on the sub-system rail.

The following design procedure can be used to select component values for the device. Alternatively, the WEBENCH® software may be used to generate a complete design. The WEBENCH® software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. Additionally, a spreadsheet design tool TPS2592 Design Calculator (SLUC571) is available on web folder. This section presents a simplified discussion of the design process.

10.2 Typical Applications

10.2.1 Simple 2.1-A eFuse Protection for Set Top Boxes

TPS2592ZA TPS2592ZL 2592Z_App_Diag_Sec_10_2_1_slvscu3.gif Figure 28. Typical Application Schematic: Simple e-Fuse for STBs

10.2.1.1 Design Requirements

Table 2. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range, VIN 12 V
Undervoltage lockout set point, V(UV) Default: VUVR = 4.3 V
Load at Start-Up , RL(SU) 4 Ω
Current limit, IOL = IILIM 2.1 A
Load capacitance , COUT 1 µF
Maximum ambient temperatures , TA 85°C

10.2.1.2 Detailed Design Procedure

The following design procedure can be used to select component values for the TPS2592xx.

10.2.1.2.1 Step by Step Design Procedure

This design procedure below seeks to control the junction temperature of device under both static and transient conditions by proper selection of output ramp-up time and associated support components. The designer can adjust this procedure to fit the application and design criteria.

10.2.1.2.2 Programming the Current-Limit Threshold: RILIM Selection

The RILIM resistor at the ILIM pin sets the over load current limit, this can be set using Equation 4.

Equation 4. TPS2592ZA TPS2592ZL eq4_lvscq3.gif

For IOL = IILIM = 2.1 A, from equation 4, RILIM = 45.3 kΩ, choose closest standard value resistor with 1% tolerance.

10.2.1.2.3 Undervoltage Lockout Set Point

The undervoltage lockout (UVLO) trip point is adjusted using the external voltage divider network of R1 and R2 as connected between IN, EN/UVLO and GND pins of the device. The values required for setting the undervoltage are calculated solving Equation 5.

Equation 5. TPS2592ZA TPS2592ZL eq5_slvscq3.gif

Where VENR = 1.4 V is enable voltage rising threshold.

Since R1 and R2 will leak the current from input supply (VIN), these resistors should be selected based on the acceptable leakage current from input power supply (VIN). The current drawnby R1 and R2 from the power supply {IR12 = VIN/(R1 + R2)}.

However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, IR12 must be chosen to be 20x greater than the leakage current expected.

For default UVLO of VUVR = 4.3 V, select R2 = OPEN, and R1 = 1 MΩ. Since EN/UVLO pin is rated only to 7 V, it cannot be connected directly to VIN = 12 V. It has to be connected through R1 = 1 MΩ only, so that the pull-up current for EN/UVLO pin is limited to < 20 µA.

The power failure threshold is detected on the falling edge of supply. This threshold voltage is 4% lower than the rising threshold, VUVR. This is calculated using Equation 6.

Equation 6. V(PFAIL) = 0.96 x VUVR

Where VUVR is 4.3V, Power fail threshold set is : 4.1 V

10.2.1.2.4 Setting Output Voltage Ramp Time (TdVdT)

For a successful design, the junction temperature of device should be kept below the absolute-maximum rating during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.

The ramp-up capacitor CdVdT needed is calculated considering the two possible cases:

10.2.1.2.4.1 Case 1: Start-up without Load: Only Output Capacitance COUT Draws Current During Start-up

During start-up, as the output capacitor charges, the voltage difference as well as the power dissipated across the internal FET decreases. The average power dissipated in the device during start-up is calculated using Equation 8.

For TPS2592xx, the inrush current is determined as,

Equation 7. TPS2592ZA TPS2592ZL eq7_lvscq3.gif

Power dissipation during start-up is:

Equation 8. TPS2592ZA TPS2592ZL eq_15_slvsce9.gif

Equation 8 assumes that load does not draw any current until the output voltage has reached its final value.

10.2.1.2.4.2 Case 2: Start-up with Load: Output Capacitance COUT and Load Draws Current During Start-up

When load draws current during the turn-on sequence, there will be additional power dissipated. Considering a resistive load during start-up (RL(SU)), load current ramps up proportionally with increase in output voltage during TdVdT time. The average power dissipation in the internal FET during charging time due to resistive load is given by:

Equation 9. TPS2592ZA TPS2592ZL eq_19_slvsce9.gif

Total power dissipated in the device during startup is:

Equation 10. TPS2592ZA TPS2592ZL eq_20_slvsce9.gif

Total current during startup is given by:

Equation 11. TPS2592ZA TPS2592ZL eq_21_slvsce9.gif

If I(STARTUP) > IOL, the device limits the current to IOL and the current limited charging time is determined by:

Equation 12. TPS2592ZA TPS2592ZL eq12_slvscq3.gif

The power dissipation, with and without load, for selected start-up time should not exceed the shutdown limits as shown in Figure 29.

TPS2592ZA TPS2592ZL D001_SLVSC11.gif Figure 29. Thermal Shutdown Limit Plot

For the design example under discussion, select ramp-up capacitor CdVdT = OPEN. Then, using Equation 2.

Equation 13. TPS2592ZA TPS2592ZL eq13_lvscq3.gif

The inrush current drawn by the load capacitance (COUT) during ramp-up using Equation 7.

Equation 14. TPS2592ZA TPS2592ZL eq14_lvscq3.gif

The inrush Power dissipation is calculated, using Equation 8.

Equation 15. TPS2592ZA TPS2592ZL eq15_lvscq3.gif

For 90 mW of power loss, the thermal shut down time of the device should not be less than the ramp-up time TdVdT to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 29 at
TA = 85°C, for 90 mW of power, the shutdown time is infinite. So it is safe to use 0.79 ms as start-up time without any load on output.

Considering the start-up with load 4 Ω, the additional power dissipation, when load is present during start up is calculated, using Equation 9.

Equation 16. TPS2592ZA TPS2592ZL eq16_lvscq3.gif

The total device power dissipation during start up is:

Equation 17. TPS2592ZA TPS2592ZL eq17_lvscq3.gif

From thermal shutdown limit graph at TA = 85°C, the thermal shutdown time for 6.09 W is more than 100 ms. So it is well within acceptable limits to use no external capacitor (CdV/dT) with start-up load of 4 Ω.

If, due to large COUT, there is a need to decrease the power loss during start-up, it can be done with increase of CdVdT capacitor.

10.2.1.3 Support Component Selection - CVIN

CVIN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for CVIN.

10.2.1.4 Application Curves

TPS2592ZA TPS2592ZL App_Plot1_slvsc11.png
Figure 30. Output Ramp without Load on Output
TPS2592ZA TPS2592ZL App_Plot2_slvsc11.png
Figure 31. Output Ramp with 4-Ω Load at Start Up

10.3 Maximum Device Power Dissipation Considerations

To prevent damage to the TPS2592x, it is necessary to keep internal power dissipation (PD) below the levels specified in below Table. The power dissipation is defined as (PD = (VIN – VOUT) x IOUT).

MIN MAX UNIT
Maximum Power Dissipation –40°C ≤ TA ≤ +85°C 40 W
0°C ≤ TA ≤ +85°C 50

During normal operation PD is low ( typically < ½ Watt) because the FET is fully on with low (VIN – VOUT). However, during short circuit and surge protection the FET may be only partially on and (VIN – VOUT) can be high.

Example 1: Short Circuit on Output → VIN = 15 V, ILIMIT = 2.1 A. TJ = –40°C

  • PD = 15 V x 2.1 A = 31.5 W
  • OK → (PD = 31.5 W) < (PD_MAX = 40 W)

Example 2: Short Circuit on Output → VIN = 18 V, ILIMIT = 2.1 A

  • PD = 18 V x 2.1 A = 37.8 W
  • OK at TJ = 0°C → (PD = 37.8 W) < (PD_MAX at 0°C = 50 W)
  • OK at TJ = –40°C → (PD = 37.8 W) > (PD_MAX at –40°C = 40 W)