SLVSCE9D June   2014  – October  2017 TPS25942A , TPS25942L , TPS25944A , TPS25944L

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Enable and Adjusting Undervoltage Lockout
      2. 9.3.2  Overvoltage Protection (OVP)
      3. 9.3.3  Hot Plug-In and In-Rush Current Control
      4. 9.3.4  Overload and Short Circuit Protection
        1. 9.3.4.1 Overload Protection
        2. 9.3.4.2 Short Circuit Protection
        3. 9.3.4.3 Start-Up With Short on Output
        4. 9.3.4.4 Constant Current Limit Behavior During Overcurrent Faults
      5. 9.3.5  Reverse Current Protection
      6. 9.3.6  FAULT Response
      7. 9.3.7  Current Monitoring
      8. 9.3.8  Power Good Comparator
      9. 9.3.9  IN, OUT and GND Pins
      10. 9.3.10 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Diode Mode
      2. 9.4.2 Shutdown Control
      3. 9.4.3 Operational Differences Between the TPS25942 and TPS25944
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Step by Step Design Procedure
        2. 10.2.2.2 Programming the Current-Limit Threshold: R(ILIM) Selection
        3. 10.2.2.3 Undervoltage Lockout and Overvoltage Set Point
        4. 10.2.2.4 Programming Current Monitoring Resistor—RIMON
        5. 10.2.2.5 Setting Output Voltage Ramp Time (tdVdT)
          1. 10.2.2.5.1 Case1: Start-Up Without Load: Only Output Capacitance C(OUT) Draws Current During Start-Up
          2. 10.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance C(OUT) and Load Draws Current During Start-Up
        6. 10.2.2.6 Programing the Power Good Set Point
        7. 10.2.2.7 Support Component Selections—R6, R7 and CIN
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Active ORing (Auto-Power Multiplexer) Operation
        1. 10.3.1.1 N+1 Power Supply Operation
        2. 10.3.1.2 Priority Power MUX Operation
        3. 10.3.1.3 Priority MUXing With Almost Equal Rails (VIN1 ~ VIN2)
        4. 10.3.1.4 Reverse Polarity Protection
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
    2. 11.2 Output Short-Circuit Measurements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Community Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Timing Requirements

Conditions are –40°C ≤ TJ = TA ≤ +125°C, 2.7 V ≤ V(IN) ≤ 18 V, V(EN/UVLO) = 2 V, V(OVP) = V(DMODE) = V(PGTH) = 0 V, R(ILIM) = 150 kΩ, C(OUT) = 1 µF, C(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise noted). See Figure 47 for timing diagrams.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ENABLE AND UVLO INPUT
tON(dly) EN turnon delay EN/UVLO ↑ (100 mV above V(ENR)) to V(OUT) = 100 mV,
C(dVdT) < 0.8 nF		 220 µs
EN/UVLO ↑ (100 mV above V(ENR)) to V(OUT) = 100 mV,
C(dVdT) ≥ 0.8 nF, see , [C(dVdT) in nF]		 100 + 150 × C(dVdT) µs
tOFF(dly) EN turnoff delay EN/UVLO ↓ (100 mV below V(ENF)) to FLT↓ 2 µs
OVERVOLTAGE PROTECTION INPUT (OVP)
tOVP(dly) OVP disable delay OVP↑ (100 mV above V(OVPR)) to FLT↓ 2 µs
DIODE MODE INPUT: ACTIVE HIGH (DMODE)
tDMODE DMODE turnon delay DMODE↓ to (V(IN) – V(OUT)) ≤ 200 mV, with 1 A resistive load at OUT 2 µs
DMODE turnoff delay DMODE↑ to (V(IN) – V(OUT)) > 200 mV, 1 A resistive load at OUT 220 ns
OUTPUT RAMP CONTROL (dVdT)
tdVdT Output ramp time EN/UVLO ↑ to V(OUT) = 4.5 V, with C(dVdT) = open 0.12 ms
EN/UVLO ↑ to V(OUT) = 11 V, with C(dVdT) = open 0.25 0.37 0.5
EN/UVLO↑ to V(OUT) = 11 V, with C(dVdT) = 1 nF 0.97
CURRENT LIMIT
tFASTRIP(dly) Fast-trip comparator delay I(OUT) > I(FASTRIP) 200 ns
REVERSE PROTECTION COMPARATOR
tREV(dly) Reverse protection comparator delay (V(IN) – V(OUT))↓ (1 mV overdrive below V(REVTH)) to FLT↓ 10 µs
(V(IN) – V(OUT))↓ (10 mV overdrive below V(REVTH)) to FLT↓ 1
tFWD(dly) (V(IN) – V(OUT))↑ (10 mV overdrive above V(FWDTH)) to FLT↑ 3.1
POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH
tPGOODR PGOOD delay (de-glitch) time TPS25942: rising edge 0.42 0.54 0.66 ms
TPS25944: rising edge 4
tPGOODF TPS25942 and TPS25944: falling edge 10 µs
FAULT FLAG (FLT)
tCB(dly) FLT assertion delay in circuit breaker mode TPS25944 only; delay from I(OUT) > I(LIM) to FLT↓ (and internal FET turned off) 4 ms
tCB(Retrydly) Retry delay in circuit breaker mode TPS25944A only; circuit breaker fault asserted, delay from to FLT↓ to FLT↑ edge 128 ms
THERMAL SHUT DOWN (TSD)
Retry delay in TSD TPS25942A and TPS25944A only 128 ms