SLVSBE9E April   2012  – June 2015 TPS27081A


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
      1. 6.6.1 PFET Q1 Minimum Safe Operating Area (SOA)
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 ON/OFF
      2. 7.4.2 Fastest Output Rise Time
      3. 7.4.3 Controlled Output Rise Time
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Standard Load Switching Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. Configuring Q1 ON Resistance
          2. Configuring Turnon Slew Rate
          3. Configuring Turnoff Delay
          4. Low Voltage ON/OFF Interface
          5. ON-Chip Power Dissipation
        3. Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Standby Power Isolation
      2. 8.3.2 Boost Regulator With True Shutdown
      3. 8.3.3 Single Module Multiple Power Supply Sequencing
      4. 8.3.4 Multiple Modules Interdependent Power Supply Sequencing
      5. 8.3.5 TFT LCD Module Inrush Current Control
      6. 8.3.6 Multiple Modules Interdependent Supply Sequencing Without a GPIO Input
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Reliability
    4. 10.4 Improving Package Thermal Performance
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The TPS27081A device is a load switch capable fo handing up to 8 V and 3 A. To reduce voltage drop for low voltage and high current rails, the device implements an ultra-low resistance P-channel MOSFET which reduces the dropout voltage through the device.

The device has a programmable slew rate which helps reduce or eliminate power supply droop due to large inrush currents. During shutdown, the device has very low leakage currents.

7.2 Functional Block Diagram

TPS27081A fbd_mls_slvsbe9.gif

7.3 Feature Description

The TPS27081A device uses a low-voltage power PMOS transistor used as the pass element or switch between the supply and load. The device also uses an NMOS transistor to turn the PMOS on and off by interfacing with a wide range of GPIO voltages. Asserting an input voltage higher than VIH (1 V) enables the PMOS switch by turning the NMOS and the NMOS driving the PMOS gate towards ground. When using R2 to control output rise time and a pullup resistor R1 to tie the gate of the PMOS to the source to ensure turnoff, be sure to use an R1 value big enough to source a small enough of current into R2 to not grossly effect the PMOS ON-state gate voltage.

TPS27081A offers additional ports to control the output rise time by connecting passive elements between these pins, VIN, and VOUT.

7.4 Device Functional Modes

7.4.1 ON/OFF

When VIN > approximately 1 V and V(ON/OFF) > 1 V, the switch turns on and VOUT ≈ VIN.

When VIN > approximately 1 V and V(ON/OFF) <1 V, the switch turns off and VOUT ≠ VIN.

7.4.2 Fastest Output Rise Time

Whenever it is desired to achieve the fastest output rise time, tie pin 1 (R2) to ground and do not put a capacitor between VOUT (pins 2 and 3) and R1 and C1 (pin 6).

7.4.3 Controlled Output Rise Time

Whenever it is desired to control the output rise time, tie pin 1 (R2) to a resistance (R2) and put a capacitor (C1) between VOUT (pins 2 and 3) and R1 and C1 (pin 6). The values needed to determine a certain output rise time can be determined by Equation 3.