SBVS419A March   2022  – September 2023 TPS3760-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 8.3.1.2 Power-On Reset (VDD < VPOR )
      2. 8.3.2 SENSE
        1. 8.3.2.1 SENSE Hysteresis
      3. 8.3.3 Output Logic Configurations
        1. 8.3.3.1 Open-Drain
        2. 8.3.3.2 Push-Pull
        3. 8.3.3.3 Active-High (RESET)
        4. 8.3.3.4 Active-Low (RESET)
      4. 8.3.4 User-Programmable Reset Time Delay
        1. 8.3.4.1 Reset Time Delay Configuration
      5. 8.3.5 User-Programmable Sense Delay
        1. 8.3.5.1 Sense Time Delay Configuration
      6. 8.3.6 Manual RESET (CTR / MR) Input
      7. 8.3.7 RESET Latch Mode
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Adjustable Voltage Thresholds
    3. 9.3 Typical Application
      1. 9.3.1 Design 1: Off-Battery Monitoring
        1. 9.3.1.1 Design Requirements
        2. 9.3.1.2 Detailed Design Procedure
        3. 9.3.1.3 Application Curves
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Power Dissipation and Device Operation
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Creepage Distance
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions


GUID-20210901-SS0I-KWVP-1MKQ-6DKLZ4S5MDJT-low.svgFigure 6-1 DYY Package,
14-Pin SOT-23,
TPS3760-Q1 (Top View)
Table 6-1 Pin Functions
PIN

SOT23 (DYY)

I/ODESCRIPTION
NAMENO.
VDD1IInput Supply Voltage: Bypass with a 0.1 µF capacitor to GND.
SENSE3I

Sense Voltage: The voltage monitored by this pin is compared to the internal voltage threshold, Vth, that is determined by an internal voltage divider for fixed variants or an external voltage divider for adjustable variants. When the SENSE pin detects a fault, RESET/RESET asserts after the sense time delay, set by CTS. When the voltage on the SENSE pin transitions back past Vth and hysteresis, VHYS, RESET/RESET deasserts after the reset time delay, set by CTR. For noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this pin may be needed for optimum performance.

Sensing Topology: Overvoltage (OV) or Undervoltage (UV)

RESET/RESET6O

Output Reset Signal: See Device Comparison for output topology options. RESET/RESET asserts when SENSE crosses the voltage threshold after the sense time delay, set by CTS. RESET/RESET remains asserted for the reset time delay period after SENSE transitions out of a fault condition. For active low open-drain reset output, an external pullup resistor is required. Do not place external pullup resistors on push-pull outputs.

Output topology: Open Drain or Push Pull, Active Low or Active High

CTS /LATCH10OSENSE Time Delay: Capacitor programmable sense delay: CTS pin offers a user-adjustable sense delay time when asserting a reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET/RESET delay time to assert.

LATCH: CTS functionality is disabled in latch capable devices. When latch mode is activated, RESET/RESET will not de-assert even if the fault is cleared. To activate latch mode, the LATCH pin has to be driven low, to at least 1.4V. It is recommended to have a 10kΩ pull-down to ground. To deactivate latch mode, a 2.1V or greater for 3µs has to be applied to the LATCH pin while SENSE pin is not detecting a fault. RESET/RESET will de-assert with delay tctr starting on the rising edge of the deactivating signal.

CTR /MR9-

RESET Time Delay: User-programmable reset time delay for RESET/RESET. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay.

Manual Reset: If this pin is driven low, the RESET/RESET output will reset and become asserted. The pin can be left floating or be connected to a capacitor. This pin should not be driven high.

GND8, 13-Ground. All GND pins must be electrically connected to the board ground.
NC2, 4, 5, 7, 11,12, 14-

NC stands for “No Connect.” The pins are to be left floating.