SLUSC89 November 2015 TPS40210-EP
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS40210-EP is a 4.5-V to 52-V low-side controller with an integrated gate driver for a low-side N-channel MOSFET. This device is typically used in a boost topology to convert a lower DC voltage to a higher DC voltage with a peak current limit set by an external current sense resistor. It can also be configured in a SEPIC, Flyback and LED drive applications. In higher current applications, the maximum current can also be limited by the thermal performance of the external MOSFET and rectifying diode switch. Use the following design procedure to select external components for the TPS40210-EP. The design procedure illustrates the design of a typical boost regulator with the TPS40210-EP. Alternatively, use the WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design.
The following example illustrates the design process and component selection for a 12-V to 24-V nonsynchronous boost regulator using the TPS40210-EP controller.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT CHARACTERISTICS | ||||||
V_{IN} | Input voltage | 8 | 12 | 14 | V | |
I_{IN} | Input current | 4.4 | A | |||
No load input current | 0.05 | |||||
V_{IN(UVLO)} | Input undervoltage lockout | 4.5 | V | |||
OUTPUT CHARACTERISTICS | ||||||
V_{OUT} | Output voltage | 23.5 | 24.0 | 24.5 | V | |
Line regulation | 1% | |||||
Load regulation | 1% | |||||
V_{OUT(ripple)} | Output voltage ripple | 500 | mV_{PP} | |||
I_{OUT} | Output current | 8 V ≤ V_{IN} ≤ 14 V | 0.1 | 1 | 2.0 | A |
I_{OCP} | Output overcurrent inception point | 3.5 | ||||
Transient response | ||||||
ΔI | Load step | 1 | A | |||
Load slew rate | 1 | A/μs | ||||
Overshoot threshold voltage | 500 | mV | ||||
Settling time | 5 | ms | ||||
SYSTEM CHARACTERISTICS | ||||||
ƒ_{SW} | Switching frequency | 600 | kHz | |||
η_{PK} | Peak efficiency | V_{IN} = 12 V | 95% | |||
η_{} | Full load efficiency | V_{IN} = 12 V, I_{OUT} = 2 A | 94% | |||
T_{OP} | Operating temperature range | 8 V ≤ V_{IN} ≤ 14 V, I_{OUT} ≤ 2 A | 25 | °C | ||
MECHANICAL DIMENSIONS | ||||||
W | Width | 1.5 | inch | |||
L | Length | 1.5 | ||||
h | Height | 0.5 |
The duty cycle of the main switching MOSFET is estimated using Equation 31 and Equation 32.
Using an estimated forward drop (V_{FD}) of 0.5V for a schottky rectifier diode, the approximate duty cycle is 42.9% (minimum) to 67.3% (maximum).
The peak-to-peak ripple is chosen to be 30% of the maximum input current.
The minimum inductor size can be estimated using Equation 34.
The next higher standard inductor value of 10 μH is selected. The ripple current for nominal and minimum V_{IN} is estimated by Equation 35 and Equation 36.
The worst case peak-to-peak ripple current occurs at 50% duty cycle (V_{IN} = 12.25 V) and is estimated as 1.02 A. Worst case RMS current through the inductor is approximated by Equation 37.
The worst case RMS inductor current is 6.13 A. The peak inductor current is estimated by Equation 38.
A 10-μH inductor with a minimum RMS current rating of 6.13 A and minimum saturation current rating of 6.57 A must be selected. A TDK RLF12560T-100M-7R5 7.5-A 10-μH inductor is selected.
This inductor power dissipation is estimated by Equation 39.
The TDK RLF12560T-100M-7R5 12.4-mΩ DCR dissipates 466-mW of power.
A low forward voltage drop schottky diode is used as a rectifier diode to reduce its power dissipation and improve efficiency. Using 80% derating on V_{OUT} for ringing on the switch node, the rectifier diode minimum reverse break-down voltage is given by Equation 40.
The diode must have reverse breakdown voltage greater than 30 V. The rectifier diode peak and average currents are estimated by Equation 41 and Equation 42.
The power dissipation in the diode is estimated by Equation 43.
For this design, the maximum power dissipation is estimated as 1 W. Reviewing 30-V and 40-V schottky diodes, the MBRS340T3, 40-V, 3-A diode in an SMC package is selected. This diode has a forward voltage drop of 0.48 V at 6 A, so the conduction power dissipation is approximately 960 mW, less than half its rated power dissipation.
Output capacitors must be selected to meet the required output ripple and transient specifications.
A Panasonic EEEFC1V330P 35-V 33-μF, 120-mΩ bulk capacitor and a 6.8-μF ceramic capacitor are selected to provide the required capacitance and ESR at the switching frequency. The combined capacitance of 39.8 μF and ESR of 60 mΩ are used in compensation calculations.
Since a boost converter has continuous input current, the input capacitor senses only the inductor ripple current. The input capacitor value can be calculated by Equation 46 and Equation 47 .
For this design to meet a maximum input ripple of 60mV (1/2% of V_{IN} nominal), a minimum 7.1-μF input capacitor with ESR less than 29mΩ is needed. A 10-μF, X7R ceramic capacitor is selected.
The maximum allowable current sense resistor value is limited by both the current limit and sub-harmonic stability. These two limitations are given by Equation 48 and Equation 49.
With 10% margin on the current limit trip point (the 1.1 factor) and assuming a maximum gate drive current of 500 mA, the current limit requires a resistor less than 15.4 mΩ and stability requires a sense resistor less than 134 mΩ. A 10-mΩ resistor is selected. Approximately 2 mΩ of routing resistance is added in compensation calculations.
The power dissipation in R_{ISNS} is calculated by Equation 50.
At maximum duty cycle, this is 0.253 W.
To remove switching noise from the current sense, an RC filter is placed between the current sense resistor and the ISNS pin. A resistor with a value between 1 kΩ and 5 kΩ is selected and a capacitor value is calculated by Equation 51.
For a 1-kΩ filter resistor, 71pF is calculated and a 100-pF capacitor is selected.
The TPS40210-EP drives a ground referenced N-channel FET. The R_{DS(on)} and gate charge are estimated based on the desired efficiency target.
For a target of 95% efficiency with a 24-V Input voltage at 2 A, maximum power dissipation is limited to 2.526 W. The main power dissipating devices are the MOSFET, inductor, diode, current sense resistor and the integrated circuit, the TPS40210-EP.
This leaves 812 mW of power dissipation for the MOSFET. This can likely cause an SO-8 MOSFET to get too hot, so power dissipation is limited to 500 mW. Allowing half for conduction and half for switching losses, we can determine a target R_{DS(on) }and Q_{GS} for the MOSFET by Equation 54 and Equation 55.
A target MOSFET gate-to-source charge of less than 13.0 nC is calculated to limit the switching losses to less than 250 mW.
A target MOSFET R_{DS(on)} of 9.9 mΩ is calculated to limit the conduction losses to less than 250 mW. Reviewing 30-V and 40-V MOSFETs, an Si4386DY 9-mΩ MOSFET is selected. A gate resistor was added per Equation 30. The maximum gate charge at V_{GS}= 8V for the Si4386DY is 33.2 nC, this implies R_{G} = 3.3 Ω.
The primary feedback divider resistor (R_{FB}) from V_{OUT} to FB should be selected between 10 kΩ and 100 kΩ to maintain a balance between power dissipation and noise sensitivity. For a 24-V output a high feedback resistance is desirable to limit power dissipation so R_{FB} = 51.1 kΩ is selected.
R_{BIAS} = 1.50kΩ is selected.
Compensation selection can be done with aid of WEBENCH to select compensation components or with the aid of the average Spice model to simulate the open loop modulator and power stage gain. Alternatively the following procedure gives a good starting point.
While current mode control typically only requires Type II compensation, it is desirable to layout for Type III compensation to increase flexibility during design and development. Current mode control boost converters have higher gain with higher output impedance, so it is necessary to calculate the control loop gain at the maximum output impedance, estimated by Equation 57.
The transconductance of the TPS40210-EP current mode control can be estimated by Equation 58.
The maximum output impedance Z_{OUT}, can be estimated by Equation 59.
At the desired crossover frequency (ƒ_{L}) of 30 kHz, Z_{OUT} becomes 0.146 Ω.
The modulator gain at the desired cross-over can be estimated by Equation 61.
The feedback compensation network needs to be designed to provide an inverse gain at the cross-over frequency for unity loop gain. This sets the compensation mid-band gain at a value calculated in Equation 62.
To set the mid-band gain of the error amplifier to K_{COMP} use Equation 63.
R4 = 18.7 kΩ selected.
Place the zero at 1/10th of the desired cross-over frequency.
C2 = 2200 pF selected.
Place a high-frequency pole at about 5 times the desired cross-over frequency and less than one-half the unity gain bandwidth of the error amplifier:
C4 = 47 pF selected.
The RC oscillator calculation is given as shown in Equation 14 in the datasheet, substituting 100 for C_{T} and 600 for ƒ_{SW}. For a 600-kHz switching frequency, a 100pF capacitor is selected and a 262-kΩ resistor is calculated (261-kΩ selected).
Since VDD > 8 V, the soft-start capacitor is selected by using Equation 67 to calculate the value.
For T_{SS} = 12 ms, C_{SS} = 240 nF. A 220-nF capacitor is selected.
A regulator bypass (BP) capacitor of 1.0 μF is selected per the datasheet recommendation.
REFERENCE DESIGNATOR |
DESCRIPTION | SIZE | PART NUMBER |
MANUFAC- TURER |
---|---|---|---|---|
C1 | 100 μF, aluminum capacitor, SM, ± 20%, 35 V | 0.406 x 0.457 | EEEFC1V101P | Panasonic |
C2 | 2200 pF, ceramic capacitor, 25 V, X7R, 20% | 0603 | Std | Std |
C3 | 100 pF, ceramic capacitor, 16 V, C0G, 10% | 0603 | Std | Std |
C4 | 47 pF, ceramic capacitor, 16V, X7R, 20% | 0603 | Std | Std |
C5 | 0.22 μF, ceramic capacitor, 16 V, X7R, 20% | 0603 | Std | Std |
C7 | 1.0 μF, ceramic capacitor, 16 V, X5R, 20% | 0603 | Std | Std |
C8 | 10 μF, ceramic capacitor, 25 V, X7R, 20% | 0805 | C3225X7R1E106M | TDK |
C9 | 0.1 μF, ceramic capacitor, 50 V, X7R, 20% | 0603 | Std | Std |
C10 | 100 pF, ceramic capacitor, 16 V, X7R, 20% | 0603 | Std | Std |
D1 | Schottky diode, 3 A, 40 V | SMC | MBRS340T3 | On Semi |
L1 | 10 μH, inductor, SMT, 7.5 A, 12.4 mΩ | 0.325 x 0.318 inch | RLF12560T-100M-7R5 | TDK |
Q1 | MOSFET, N-channel, 40 V, 14 A, 9mΩ | SO-8 | Si4840DY | Vishay |
R3 | 10 kΩ, chip resistor, 1/16 W, 5% | 0603 | Std | Std |
R4 | 18.7 kΩ, chip resistor, 1/16 W, 1% | 0603 | Std | Std |
R5 | 1.5 kΩ, chip resistor, 1/16 W, 1% | 0603 | Std | Std |
R6 | 261 kΩ, chip resistor, 1/16 W, 1% | 0603 | Std | Std |
R7 | 51.1 kΩ, chip resistor, 1/16 W, 1% | 0603 | Std | Std |
R9 | 3.3 Ω, chip resistor, 1/16 W, 5% | 0603 | Std | Std |
R10 | 1.0 kΩ, chip resistor, 1/16 W, 5% | 0603 | Std | Std |
R11 | 10 mΩ, chip resistor, 1/2 W, 2% | 1812 | Std | Std |
U1 | IC, 4.5 V-52 V I/P, current mode boost controller | DGQ10 | TPS40210-EPDGQ | TI |