SLVS947C October 2009 – August 2014 TPS53125

PRODUCTION DATA.

- 1 Features
- 2 Applications
- 3 Description
- 4 Simplified Schematics
- 5 Revision History
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information

- RGE|24

The TPS53125 is a Dual D-CAP2™ Mode Control Step-Down Controller in a realistic cost-sensitive application. Providing both a low core-type 1.05 V and I/O type 1.8 V output from a loosely regulated 12 V source. Idea applications are: Digital TV Power Supply, Networking Home Pin, Digital Set-Top Box (STB), DVD Player/Recorder, and Gaming Consoles.

PARAMETERS | EXAMPLE VALUES |
---|---|

Input voltage | 12 V |

Output voltage | VO1 = 1.8 V, VO2 = 1.05 V |

The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load. Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation.

Equation 3 can be used to calculate L1.

Equation 3.

The inductors current ratings needs to support both the RMS (thermal) current and the Peak (saturation) current. The RMS and peak inductor current can be estimated as follows.

Equation 4.

Equation 5.

Equation 6.

Note: The calculation above shall serve as a general reference. To further improve transient response, the output inductance could be reduced further. This needs to be considered along with the selection of the output capacitor.

The capacitor value and ESR determines the amount of output voltage ripple and load transient response. it is recommended to use a ceramic output capacitor.

Equation 7.

Equation 8.

Equation 9.

Where

Equation 10.

Select the capacitance value greater than the largest value calculated from Equation 7, Equation 8 and Equation 9. The capacitance for C1 should be greater than 66 μF.

Where

ΔV_{OS} = The allowable amount of overshoot voltage in load transition

ΔV_{US} = The allowable amount of undershoot voltage in load transition

T_{min(off)} = Minimum off time

The TPS53125 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A minimum 10-μF high-quality ceramic capacitor is recommended for the input capacitor. The capacitor voltage rating needs to be greater than the maximum input voltage.

The TPS53125 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the high-side drivers. A minimum 0.1-μF high-quality ceramic capacitor is recommended. The voltage rating should be greater than 10 V.

The TPS53125 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-μF high-quality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A minimum 1-μF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper operation. Both of these capacitors’ voltage ratings should be greater than 10 V.

The output voltage is set with a resistor divider from the output voltage node to the VFBx pin. It is recommended to use 1% tolerance or better resisters. Select R2 between 10 kΩ and 100 kΩ and use Equation 11 or Equation 12 to calculate R1.

Equation 11.

Equation 12.

Where

V_{FB(RIPPLE)} = Ripple voltage at VFB

V_{swinj} = Ripple voltage at error comparator

Equation 13.

Equation 14.

Where

R_{DS(ON)} = Low side FET on-resistance

I_{TRIP(min)} = TRIP pin source current （8.5 μA）

V_{OCL0ff} = Minimum over current limit offset voltage (–20 mV)

I_{OCL} = Over current limit

Soft start time equation is as follows.

Equation 15.

I_{O}1 = 3 A |
V_{O}1 = 1.8 V |

VIN = 12 V | V_{O}1 = 1.8 V |

VIN = 12 V | V_{O}1 = 1.8 V |

VIN = 12 V | V_{O}1 = 1.85 V |

V_{O}1 = 1.8 V |

V_{O}1 = 1.8 V |

I_{O}2 = 3 A |
V_{O}2 = 1.05 V |

VIN = 12 V | V_{O}2 = 1.05 V |

VIN = 12 V | V_{O}2 = 1.05 V |

VIN = 12 V | V_{O}2 = 1.05 V |

V_{O}2 = 1.05 V |

V_{O}2 = 1.05 V |

The TPS53125 is a Dual D-CAP2™ Mode Control Step-Down Controller in a realistic cost-sensitive application. Providing both a low core-type 1.05 V and I/O type 1.8V output from a loosely regulated 12 V source.

For the Design Requirements, refer to Design Requirements (QFN).

For the Detailed Design Procedure, refer to Detailed Design Procedure (QFN).

For Application Curves, refer to Application Curves (QFN).