SLUSAU4B DECEMBER 2011 – February 2019 TPS53219A
When the EN pin voltage rises above the enable threshold voltage (typically 1.4 V), the controller enters its start-up sequence. The internal LDO regulator starts immediately and regulates to 6.2 V at the VREG pin. The controller then uses the first 250 µs to calibrate the switching frequency setting resistance attached to the RF pin and stores the switching frequency code in internal registers. However, switching is inhibited during this phase. In the second phase, an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. Depending on the MODE pin setting, the ramping up time varies from 0.7 ms to 5.6 ms. Smooth and constant ramp-up of the output voltage is maintained during start-up regardless of load current.
|Auto Skip||Pull down to GND||0.7||39|
|Forced CCM (1)||Connect to PGOOD||0.7||39|
When the EN voltage is higher than 5.5 V, a 1-kΩ series resistor is needed for EN pin