SLUSAU4B DECEMBER   2011  – February 2019 TPS53219A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Soft-Start
      2. 7.3.2  Adaptive ON-Time D-CAP Control and Frequency Selection
      3. 7.3.3  Small Signal Model
      4. 7.3.4  Ramp Signal
      5. 7.3.5  Adaptive Zero Crossing
      6. 7.3.6  Output Discharge Control
      7. 7.3.7  Low-Side Driver
      8. 7.3.8  High-Side Driver
      9. 7.3.9  Power Good
      10. 7.3.10 Current Sense and Overcurrent Protection
      11. 7.3.11 Overvoltage and Undervoltage Protection
      12. 7.3.12 UVLO Protection
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Condition in Auto-Skip Operation
      2. 7.4.2 Forced Continuous Conduction Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application With Power Block
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 External Components Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application With Ceramic Output Capacitors
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 External Parts Selection With All Ceramic Output Capacitors
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Enable and Soft-Start

When the EN pin voltage rises above the enable threshold voltage (typically 1.4 V), the controller enters its start-up sequence. The internal LDO regulator starts immediately and regulates to 6.2 V at the VREG pin. The controller then uses the first 250 µs to calibrate the switching frequency setting resistance attached to the RF pin and stores the switching frequency code in internal registers. However, switching is inhibited during this phase. In the second phase, an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. Depending on the MODE pin setting, the ramping up time varies from 0.7 ms to 5.6 ms. Smooth and constant ramp-up of the output voltage is maintained during start-up regardless of load current.

Table 1. Soft-Start and MODE

MODE
SELECTION		 ACTION SOFT-START
TIME (ms)		 RMODE (kΩ)
Auto Skip Pull down to GND 0.7 39
1.4 100
2.8 200
5.6 475
Forced CCM (1) Connect to PGOOD 0.7 39
1.4 100
2.8 200
5.6 475
(1) Device goes into Forced CCM after PGOOD becomes high.

When the EN voltage is higher than 5.5 V, a 1-kΩ series resistor is needed for EN pin