SLUSEL9 June   2021 TPS53689


  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Device and Documentation Support
    1. 5.1 Documentation Support
      1. 5.1.1 Related Documentation
    2. 5.2 Receiving Notification of Documentation Updates
    3. 5.3 Support Resources
    4. 5.4 Trademarks
    5. 5.5 Electrostatic Discharge Caution
    6. 5.6 Glossary
  6. 6Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


  • Input voltage range: 4.5 V to 17 V
  • Output voltage range: 0.25 V to 5.5 V
  • Dual output supporting N+M phase configurations (N+M ≤ 8, M ≤ 4)
  • Intel® VR14 SVID compliant with PSYS support
  • Backward compatible to VR13.HC/VR13.0 SVID
  • Automatic NVM fault status logging
  • Dynamic current limit for improved Fast-Vmode performance
  • Fully compatible with TI NexFET™ power stage for high-density solutions
  • Enhanced D-CAP+ control to provider superior transient performance with excellent dynamic current sharing
  • Dynamic phase shedding with programmable thresholds for optimizing efficiency at light and heavy loads
  • Configurable with non-volatile memory (NVM) for low external component count
  • Accurate, adjustable, adaptive voltage positioning (AVP, load line) support
  • Individual per-phase IMON calibration, with multi-slope gain calibration to increase system accuracy.
  • Fast phase-adding for transient undershoot reduction
  • Diode braking with programmable timeout for reduced transient overshoot
  • Patented AutoBalance™ current sharing
  • Programmable per-phase valley current limit (OCL)
  • PMBus™ v1.3.1 system interface for telemetry of voltage, current, power, temperature, and fault conditions
  • Programmable loop compensation through PMBus
  • Driverless configuration for efficient high- frequency switching
  • 5.00 mm × 5.00 mm, 40-pin, QFN package