SLUSEZ6 December   2022 TPS536C5

PRODUCTION DATA  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Device and Documentation Support
    1. 5.1 Documentation Support
      1. 5.1.1 Related Documentation
    2. 5.2 Receiving Notification of Documentation Updates
    3. 5.3 Support Resources
    4. 5.4 Trademarks
    5. 5.5 Electrostatic Discharge Caution
    6. 5.6 Glossary
  6. 6Mechanical, Packaging, and Orderable Information
    1. 6.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TPS536C5 is a fully AMD SVI3 compliant step-down controller with dual channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ smart power stage. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response, low output capacitance, and good current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of VCORE slew rate and voltage positioning round out the AMD SVI3 features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.

The TPS536C5 device if offered in a thermally enhanced 48-pin QFN packaged and is rated to operate from –40°C to 125°C.

Device Information
PART NUMBER(1) PACKAGE BODY SIZE (NOM)
TPS536C5 QFN (48) 6.00 × 6.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.