SLVSB55C May   2012  – October 2015 TPS54140A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-mode
      4. 7.3.4  Bootstrap Voltage (BOOT)
      5. 7.3.5  Low Dropout Operation
      6. 7.3.6  Error Amplifier
      7. 7.3.7  Voltage Reference
      8. 7.3.8  Overload Recovery Circuit
      9. 7.3.9  Overcurrent Protection and Frequency Shift
      10. 7.3.10 Power Good (PWRGD Pin)
      11. 7.3.11 Overvoltage Transient Protection
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with VIN < 3.5 V (Minimum VIN)
      2. 7.4.2 Operation with EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting the Output Voltage
      2. 8.1.2 Enable and Adjusting Undervoltage Lockout
      3. 8.1.3 Slow Start/Tracking Pin (SS/TR)
      4. 8.1.4 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      5. 8.1.5 Selecting the Switching Frequency
      6. 8.1.6 How to Interface to RT/CLK Pin
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Switching Frequency
        2. 8.2.2.2  Output Inductor Selection (LO)
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Catch Diode
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Slow Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Undervoltage Lock Out Set Point
        9. 8.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 8.2.2.10 Compensation
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Simple Small Signal Model for Peak Current Mode Control
      2. 8.3.2 Small Signal Model for Frequency Compensation
      3. 8.3.3 Small Signal Model for Loop Response
  9. 9 Power Supply Recommendations
    1. 9.1 Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Estimate
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 65 for a PCB layout example. The GND pin should be tied directly to the power pad under the IC and the power pad.

The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH connection is the switching node, the catch diode and output inductor should be located very close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.

10.2 Layout Example

TPS54140A layout_lvs795.gif Figure 65. PCB Layout Example

10.3 Power Dissipation Estimate

The following formulas show how to estimate the device power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM).

The power dissipation of the device includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and supply current (Pq).

Equation 54. TPS54140A q_pcond_lvs795.gif
Equation 55. TPS54140A q_psw_lvs795.gif
Equation 56. TPS54140A q_pgd_lvs795.gif
Equation 57. TPS54140A q_pq_lvs795.gif

where

  • IOUT is the output current (A)
  • RDS(on) is the on-resistance of the high-side MOSFET (Ω)
  • VOUT is the output voltage (V)
  • VIN is the input voltage (V)
  • ƒSW is the switching frequency (Hz)
Equation 58. TPS54140A q_ptot_lvs795.gif

For given TA,

Equation 59. TPS54140A q_tj_lvs795.gif

For given TJMAX = 150°C

Equation 60. TPS54140A q_tamax_lvs795.gif

where

  • PTOT s the total device power dissipation (W)
  • TA is the ambient temperature (°C)
  • TJ is the junction temperature (°C)
  • RTH is the thermal resistance of the package (°C/W)
  • TJ(max) is maximum junction temperature (°C)
  • TA(max) is maximum ambient temperature (°C).

There are additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode and trace resistance that will impact the overall efficiency of the regulator.